Abstract: A method for producing theanine including reacting a glutamic acid alkyl ester represented by general Formula (1): where R1 represents an alkyl group, with a ketone represented by general Formula (2): where R2 represents a hydrogen atom, R3 represents a lower alkanoyl group or a benzoyl group, and R2 and R3 may form a cycloalkanone ring in combination with the vicinal carbon atom, in the presence of t-butylamine, a secondary amine or a tertiary amine, reacting the resultant compound represented by general Formula (3): where R1, R2 and R3 are the same as defined above, with ethylamine, and then being subjected to heating in the presence of the ethylamine or reaction with a fatty acid.

Abstract: A disposable absorbent article comprises a containment assembly comprising a topsheet, a backsheet and an absorbent core disposed between the topsheet and the backsheet. The backsheet comprises a nonwoven web positioned at the outermost portion of the absorbent article. The backsheet covers at least a portion of the outermost portion of the absorbent core of the article. The backsheet includes a nonwoven web, which is a spunbonded nonwoven web. The spunbonded nonwoven web has a tensile strength of at least 180 gf/cm in the traverse direction of the disposable absorbent article. The backsheet further comprises a plastic film having an outer-facing surface and a body-facing surface, and the nonwoven web is joined with the outer-facing surface of the plastic film to form a laminate.

Abstract: A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.

Abstract: A method for producing theanine including reacting a glutamic acid alkyl ester represented by general Formula (1): where R1 represents an alkyl group, with a ketone represented by general Formula (2): where R2 represents a hydrogen atom, R3 represents a lower alkanoyl group or a benzoyl group, and R2 and R3 may form a cycloalkanone ring in combination with the vicinal carbon atom, in the presence of t-butylamine, a secondary amine or a tertiary amine, reacting the resultant compound represented by general Formula (3): where R1, R2 and R3 are the same as defined above, with ethylamine, and then being subjected to heating in the presence of the ethylamine or reaction with a fatty acid.

Abstract: A half-rate clock and data recovery circuit includes a phase detector capable of operating at a half-rate, a charge pump circuit, a low pass filter, and a voltage controlled oscillator. The phase detector includes a selector circuit which receives uninverted and inverted signals from respective latches of the phase detector and an uninverted and inverted half-rate clock and outputs uninverted and inverted retimed signals supplied to the charge pump so that the charge pump produces a full-rate output in response to a half-rate input. The circuit provides greater operating margin.

Abstract: A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.

Abstract: The present invention is directed to a disposable absorbent article. The disposable absorbent article of the present invention includes a fluid storage layer disposed between the topsheet and backsheet and having a body-facing surface and a garment-facing surface opposing the body-facing surface. The fluid storage layer contains a superabsorbent material. The disposable absorbent article further includes an odor reduction layer disposed at either the body-facing surface side or the body-facing surface side of the fluid storage layer. The odor reduction layer contains a metalphthalocyanine material. The disposable absorbent article further includes an isolation means disposed between the superabsorbent material and the odor reduction layer for isolating the metalphthalocyanine material from contacting at least a part of the superabsorbent material.

Abstract: The present invention is directed to a disposable absorbent article. The disposable absorbent article of the present invention includes a fluid storage layer disposed between the topsheet and backsheet and having a body-facing surface and a garment-facing surface opposing the body-facing surface. The fluid storage layer contains a superabsorbent material. The disposable absorbent article further includes an odor reduction layer disposed at either the body-facing surface side or the body-facing surface side of the fluid storage layer. The odor reduction layer contains a metalphthalocyanine material. The disposable absorbent article further includes an isolation means disposed between the superabsorbent material and the odor reduction layer for isolating the metalphthalocyanine material from contacting at least a part of the superabsorbent material.

Abstract: A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.

Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.

Abstract: A phase detector capable of operating at a half rate in a half-rate clock and data recovery (CDR) circuit includes a first latch circuit which receives an input signal, an inverted input signal and a half-rate clock, a second latch circuit which receives a first output signal and an inverted first output signal from the first latch circuit and an inverted half-rate clock, a further first latch circuit which receives the input signal, the inverted input signal and the inverted half-rate clock, a further second latch circuit which receives a further first output signal and an inverted further first output signal form the further first latch circuit and the half-rate clock, a selector circuit which receives the first output signal and the inverted first output signal and the further first output signal and the inverted further first output signal, the half-rate clock and the inverted half-rate clock so as to output a retimed signal and an inverted retimed signal and an exclusive OR circuit which receives a secon

Abstract: A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.

Abstract: In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.

Abstract: A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Abstract: A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.

Abstract: First to third D flip-flops, fourth to sixth D flip-flops, and a delay circuit are provided. The first to third D flip-flops frequency-divide a clock signal. The fourth to sixth D flip-flops are provided corresponding to the first to third D flip-flops for latching frequency-divided outputs from corresponding D flip-flops and outputting them in synchronization with the clock signal. Accordingly, the frequency-divided outputs from the fourth to sixth D flip-flops are synchronized with the clock signal with a delay of prescribed time. The delay circuit outputs the clock signal after a delay of the prescribed time. Thus, the output of the delay circuit and the frequency-divided outputs are synchronized without delay.

Abstract: A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

Abstract: A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Abstract: According to a structure in which each transistor of an output buffer transistor group of a gate array structure is electrically isolated, each body potential is set independent Also, a diode-connected transistor is provided between power supplies. An element not used in the output buffer transistor group can be connected without short-circuiting power supply lines between independent power supply lines to form an electrostatic protection circuit that is efficient in layout.

Abstract: A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.