Abstract: An object is to obtain an amplification circuit which provides a high gain even with a low-voltage power supply. The amplification circuit comprises an MOS transistor (M1) having a gate receiving an amplified signal (RFin), a source electrically connected to ground, and a drain electrically connected to a supply voltage (VDD), wherein the back gate-source voltage (Vbs) of the MOS transistor (M1) is made larger as the gate-source voltage (Vgs) of the MOS transistor (M1) becomes larger, thereby making the threshold voltage (VT) of the MOS transistor (M1) smaller.

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Abstract: MOS devices are formed on a wafer having a thick silicon layer 3a and a thin silicon layer 3b formed on a buried oxide film. The MOS device formed in the thick silicon layer 3a is activated in a partial depletion type mode. Further, the MOS device formed in the thick silicon layer 3b is activated in a perfect depletion type mode. Therefore, a low leakage current and a high-speed operation can be achieved simultaneously. It is thus possible to solve problems that an integrated circuit must be formed by either one of the partial depletion type device and the perfect depletion type device, and the low leakage current and the high-speed operation are hard to come to fruition simultaneously.

Abstract: Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption.

Abstract: A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.

Abstract: A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Abstract: In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers.

Abstract: A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

Abstract: A crystalline thermoplastic resin composition comprises a rosin acid metallic salt and a crystalline thermoplastic resin. Optionally, a compatibilizing agent may also be included. The rosin acid metallic salt, which acts as a crystal nucleating agent, increases the crystallization rate of the crystalline thermoplastic resin and enables the formation of fine crystals of the resin. Thus, the crystalline thermoplastic resin composition can crystallize at a high rate, and provide molded articles having excellent mechanical properties and/or optical properties.

Abstract: An N-type well region (NW) is provided on a P-type bulk silicon substrate (PS), and a channel region (PC) is provided inside the N-type well region (NW). The channel region is formed of a semiconductor layer having a polarity opposite to that of a source region (ST) and a drain region (DT). A contact hole (CHC) is provided in a gate oxide film (GO) located below a main portion (MP) close to an end portion (EP) of a gate electrode (GT). With this construction, a semiconductor device in which a body terminal is connected to a gate terminal for fast operation can remove restriction on location for connecting the body terminal and the gate terminal to achieve size-reduction and overcome disadvantages due to restriction on supply voltage.

Abstract: A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).

Abstract: First emitters of a pair of input multi-emitter transistors are connected to a current source in common, to form an input differential amplifier. The other emitters of the input multi-emitter transistors are connected to current sources respectively. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input multi-emitter transistors, while those of the pull-down transistors are supplied with voltages of the other emitters of the multi-emitter transistors. Provided is an emitter-coupled logic circuit which has excellent load drivability, operates stably and obtains complementary outputs at a low cost.

Abstract: A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.

Abstract: In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers.

Abstract: A counter circuit provides select signals SEL0-SEL3 of a cycle 4Tc sequentially attaining a high level for every 1/4 cycle Tc. A 4-input selector circuit receives data signals I0-I3 of a cycle 4Tc to sequentially output the same for every 1/4 period of Tc in response to a high level of select signals SEL0-SEL3. A flipflop circuit fetches and outputs an output of the selector circuit in synchronization with a clock signal C0. The number of hardware components is reduced in comparison with the conventional case where a select signal generation circuit generates only one select signal SEL, and where a plurality of flipflop circuits and 2-input selector circuits carry out a select and shifting operation of parallel data signals I0-I3.

Abstract: An emitter-coupled logic circuit having superior drivability, stable operation, and obtaining complementary outputs. A pair of input differential transistors have their emitters coupled to a first current source in common, their bases connected to receive respective input signals, and outputting complementary logic values corresponding to the respective input signals. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input transistors and their emitters are connected to the respective output terminals. The bases of the pull-down transistors are supplied with the respective input signals, their emitters are coupled to a second current source in common, and their collectors are connected to the respective output terminals. A stabilizing circuit is connected to the respective output terminals to maintain the pull-up transistors in conducting states.

Abstract: A first current switch circuit 1a outputs a first logic signal and a complementary signal thereof in response to an input logic signal. A pull-up transistor Q10 has a base receiving the first logic signal. A second current switch circuit 1b outputs a second logic signal based on the complementary signal and the potential of an output terminal OUT1. A level shift circuit 1c shifts the level of the second logic signal and provides it to the base of a pull-down transistor Q11. When the potential of an input terminal IN1 changes from a low level to a high level, a capacitive load CL is discharged through transistors Q9 and Q11. When the potential of output terminal OUT1 becomes lower than that of a first reference potential terminal VBB1, the second logic signal attains a low level, thereby turning off pull-down transistor Q11.

Abstract: There is disclosed a semiconductor integrated circuit comprising pass transistor circuits (PT3, PT4) for producing logically complementary signals. The output of the pass transistor circuit (PT3) is connected to the base electrode of an NPN bipolar transistor (BN1), and the output of the pass transistor circuit (PT4) is connected to the gate electrode of an NMOS transistor (MN9). PMOS transistors (MP15, MP16) are connected between the outputs of the pass transistor circuits (PT3, PT4) and a first potential (VDD). The gate electrodes of the PMOS transistors (MP15, MP16) are connected to the outputs of the pass transistor circuits (PT3, PT4). The bipolar transistor (BN1) having a large driving force charges and discharges a load capacity (CL1) connected to an output terminal in response to the output signal of the pass transistor circuit (PT3). This provides for a logic circuit which operates at high speeds in the semiconductor integrated circuit.