Abstract: A CMOS gate circuit constituting the input stage of a semiconductor logic circuit includes a p channel MOS transistor supplied with current from a first power supply potential Vdd for charging an output signal line to a high level potential, a diode provided between MOS transistor and output signal line, an n channel MOS transistor supplied with current from a second power supply potential Vss responsive to an input signal (Vin) for discharging the potential of output signal line, and a diode provided between MOS transistor and output signal line. An input signal potential applied to input stage has its logic amplitude set to be Vdd-Vf to Vf. Vf represents the forward voltage of the diodes and the second power supply potential is set to be ground potential GND. The input signal potential has its logic amplitude limited, current flows through the diodes in its steady state, and, therefore, the logic amplitude of the signal potential Vout of output signal line becomes Vdd-Vf to Vf.

Abstract: In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.

Abstract: Disclosed is a semiconductor integrated circuit device of a gate array system making it possible to mount a digital circuit and a high-precision analog circuit on a common substrate. This semiconductor integrated circuit device includes a basic cell array formed by a plurality of NMOS transistors and a plurality of PMOS transistors formed in rows on a semiconductor substrate. The basic cell array includes a plurality of N well regions formed in rows on the semiconductor substrate, P well regions and well terminal regions. The P well regions or N well regions are divided into small regions of the other conductivity type.

Abstract: A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width.

Abstract: A logic circuit includes an output pull up npn bipolar transistor (15; 28; 38), an output pull down pnp bipolar transistor (16; 29; 39), a first insulated gate type transistor (11, 12; 21, 22, 23, 24; 31, 32, 33, 34) for controlling the base potential of the output pull up bipolar transistor in response to an input signal, a second insulated gate type transistor (14; 25, 26, 27; 35, 36, 37) for controlling the base potential of the output pull down bipolar transistor in response to the input signal, and an impedance element (13; 18; 30; 40) for short-circuiting the base and the collector of the output pull down bipolar transistor. The impedance element is separated from the signal input terminal, and is formed by a resistance or an insulated gate type transistor operating in response to the base potential of the pull up transistor. The output pull up and pull down transistors both have collector grounded arrangement.

Abstract: A superconducting integrated circuit device switches the state of a Josephson junction element in response to incident light by diverting a current to a superconducting control signal line from a superconducting control signal extracting line. The control signal extracting line becomes resistive when irradiated by a light.

Abstract: Nuclear fuels, such as uranium trioxide, are prepared by thermal decomposition of a nitrate in a fluidized bed reactor. The fluidized bed reactor for preparing uranium trioxide from uranyl nitrate by thermal decomposition has (a) a rectangularly shaped bed which satisfies the critical safety shape of .sup.235 U, (b) plural holes to supply an aqueous solution of uranyl nitrate into the reactor, (c) at least two reaction rooms divided by barriages, the bottoms of the barriers being capable of being lifted to control their distance from the floor and a mechanism by which uranium trioxide powder is taken out mainly by being overflowed from the top of the barriers through the reaction rooms, (d) heating means inside and outside of the fluidized-bed, and (e) a head structure which is upwardly V-shaped. Continuous operation can be attained with ease, and uranium trioxide can be made efficiently.