Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A low power test circuit and a semiconductor integrated circuit are provided, i.e., the low power test circuit comprises a first stage single phase scan flip flop, a second stage single phase scan flip flop, a delay element located between an output terminal of the first stage single phase scan flip flop and an input terminal of the second stage single phase scan flip flop, a gate circuit connected between the output terminal of the first stage single phase scan flip flop and the delay element, and the gate circuit transferring scan data from the output terminal of the first stage single phase scan flip flop to the delay element in a scanning test mode thus reducing power dissipation in the delay element. The semiconductor integrated circuit comprises a shift register comprising a plurality of single phase scan flip flop serially connected and the low power test circuit.

Abstract: A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.

Abstract: A semiconductor integrated circuit has a CPU for executing various processes, at least one hardware module for receiving instructions from the CPU and executing the instructions, and a power management device for controlling the supply of a clock signal to the CPU so as to stop the clock signal to the CPU if the CPU has an idle time to start the next process. The power management device stops the supply of the clock signal to the CPU during a period in which the CPU can sleep, thereby reducing the power consumption of the CPU.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: A logic circuit design equipment has a state analysis section, a leakage current analysis section, and a cell substitution section. The state analysis section has a function of analyzing input states of all of first cells, respectively. The leakage current analysis section has a function of analyze leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively. The cell substitution section has a function of substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Abstract: An automatic circuit generation system for generating an object circuit by the use of a cell library including logic cells is described. The system comprising a node state analyzing unit which is configured to obtain combinations of input signals to exchangable input pins of a logic cell of the cell library included in the object circuit and the probabilities of the respective combinations of the input signals; a leakage current estimating unit which is configured to determine a combination of the input signals, with which the leakage current passing through the logic cell of the cell library included in the object circuit is minimized, with reference to information about leakage currents passing through the exchangable input pins of the logic cell of the cell library included in the object circuit; and an output unit which is configured to output circuit information in accordance with the combination of the input signals as obtained by the leakage current estimating unit.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: There are disclosed a multi power supply integrated circuit evaluating method which is capable of detecting power supply voltage illegal connection, redundant connection, and potential redundant connection from connection descriptions contained in a multi power supply integrated circuit in the stage of circuit design and then correcting automatically such connections, and a system for embodying the same.

Abstract: A bus (9) is structured to reduce Dower consumption. The bus (9) is used to transfer data among functional blocks (1, 3, 5, 7) formed on an LSI chip. The bus is divided into subsections (9a, 9b, 9c). A pair of the functional blocks (1, 7) whose frequency of mutual data transfer is high is connected to the same subsection (9b). Connectors (29, 31) are inserted between the subsections so that the subsections may optionally electrically be connected to and disconnected from each other. When data is transferred between the functional blocks whose frequency of mutual data transfer is high, the subsection to which the functional blocks in question are connected is electrically disconnected by the connectors from the other subsections.

Abstract: A combinational logic circuit having at least one primary input terminal and at least one primary output terminal comprises a plurality of VDDH gates having an input node and an output node and operated by a standard operating voltage and a plurality of VDDL gates having an input node and output node and operated by an operating voltage which is lower than the standard operating voltage. At least one of the VDDH gates is multiple input gate. An output node of the VDDH gate or primary input terminal operated by the standard operating voltage is connected to at least one of the input nodes of the multiple input gate. The VDDL gate or the primary output terminal operated at the operating voltage which is lower than the standard operating voltage is connected to at least one of the other input nodes of the multiple input gate through a level converter.

Abstract: A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).

Abstract: A power estimator calculates the total power consumption of a microprocessor having a CPU 5, a main memory 1 and a plurality of cache memories 2, 3 and 4 based on an assembler description of a program and calculates power consumption values when an instruction to be executed by the CPU 5 is read from a main memory 1 and when an instruction is read from the cache memories 2, 3 and 4, determines whether the instruction to be executed is read from a memory and then calculates the total power consumption for the microprocessor by using power consumption values for the memories based on the result and the power consumption value obtained for each memory.

Abstract: A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.