Abstract: The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered just adjacent to the primary output terminals.

Abstract: A clock signal generator inputs a main system clock signal and timing signals to indicate optimum timings for selecting and outputting data, respectively, in an integrated circuit to be accessed which performs based on a specified clock signal with respect to the main clock signal. The clock signal generator outputs clock signals having different duty ratios of the main clock signal according to the timing signals for a precharge operation and a readout operation for the integrated circuit. A precharge type integrated circuit including the clock signal generator outputs data therein correctly according to an address signal and the timing signals from the clock signal generator.

Abstract: The power consumption by a combinational logic circuit having primary input and output terminals is reduced. The constituent gates of the combinational logic are clustered in terms of the operating voltage levels thereof. First, the gates driven with the highest operating voltage are clustered just adjacent to the primary input terminals. Next, the gates driven with the next higher voltage are clustered adjacent to the primary input terminals only through the gates driven with the highest voltage, followed by repetition of the same clustering procedure in the order of the operating voltage level. Finally, the gates driven with the lowest operating voltage are clustered Just adjacent to the primary output terminals.

Abstract: A memory cell is provided for use in a multi-port RAM. In addition to a flip-flop circuit for memorizing data and a transfer gate for transmitting data into the flip-flop, at least a transistor series having a first, a second, and a third field effect transistors are provided. These transistors are series connected between a bit line of said RAM and a low electric supply so as to read out data from said flip-flop circuit within a short period.

Abstract: A pipeline circuit adopted for a CPU or a microprocessor in a computer system, computes the effective branch destination address of a conditional branch instruction before or in parallel with the execution of the conditional branch instruction, judges according to a result of the execution of an instruction just before the conditional branch instruction whether or not a branch condition of the conditional branch instruction is met, and, if the branch condition is met, executes the conditional branch instruction while prefetching and decoding an instruction located at the branch destination address.

Abstract: A semiconductor logic circuit for realizing bit expansion comprises a series of CMOS transfer gates that transfer, for example, a fourth bit of input data to all bit positions upper than the fourth bit. The transfer of the fourth bit is done through clocked inverters. Each of the clocked inverters gives the fourth bit to, for instance, four of the upper bit positions in parallel.

Abstract: Disclosed is a precharged-type logic circuit comprising dummy precharge lines connected to a load capacitance that is equivalent to the maximum or still larger as compared with load capacitances of respective precharge lines, wherein a precharge completion time of the dummy precharge lines is detected as a precharge completion time of the precharge lines, so that the precharge operation of the precharge lines is stopped under state of the dummy precharge line.

Abstract: A programmable logic array PLA is operated under control of a single-phase clock in which a fixed current does not flow in one of an AND array and an OR array in the PLA while the other of the AND array and the OR array is precharged. Thus, this PLA can realize low consumption of electric power and a high clock frequency, thereby enabling high-speed operation.

Abstract: Programmable logic arrays (PLAs) in the form of a matrix having each array column consisting of a plurality of FETs (Field Effect Transistors) in which cell arrays constituting each array column for producing logical product output signals are divided into a plurality of array blocks so as to reduce the number of the FETs to be connected in series in each array block and to eventually reduce the series resistance of each of the array columns, and the output signals from each of the array blocks thus divided are applied to the input terminals of each logical circuit so as to reduce each combined logical product from each logical gate, thereby realizing high speed operation for the PLAs.

Abstract: A programmable logic array comprises an input decoder having a plurality of paired first transistors inputting signals and connected in series to each other, the input decoder outputting predetermined logic signals through the first transistors based on the input signals and inverted input signals thereof; second transistors for supplying the logic output signals of the input decoder to corresponding input lines in an AND array region; and third transistors for predischarging the input lines of the AND array region.