Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers and a gate structure. The gate structure includes an outer spacer, an inner spacer and a gate electrode. The outer spacer has at least two opposite inner sidewalls to define a gate trench. The inner spacer is within the gate trench. The gate electrode disposed in the gate trench and covered by the inner spacer, wherein the inner spacer and the gate electrode extend downward to collaboratively form a bottom portion of the gate structure with a first width greater than a second width of a bottom surface of the gate electrode.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Abstract: An acupuncture stimulation system comprises a skin overlaying component and a strap having hook-and-loop fastener material, the strap can be wrapped around the skin overlaying component to snugly secure a portion of the system.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Abstract: A knee brace for continual electro-acupuncture stimulation system comprises a first circuit having a first circuit having a first electrode configured to electrically coupled to acupuncture point “Heting (S 156)” and a second electrode configured to electrically coupled to acupuncture point “Bladder 40”, a second circuit having a third electrode configured to electrically coupled to acupuncture point “Spleen 10” and a fourth electrode configured to electrically coupled to acupuncture point “Hsiyen (S 145)”, and a third circuit having a fifth electrode configured to electrically coupled to acupuncture point “Stomach 34” and a sixth electrode configured to electrically coupled to acupuncture point “Stomach 35”. The first, third, and fifth electrodes are connected to a polarity of voltage, and the second, fourth, and sixth electrodes are connected to an opposite polarity of voltage, such that electric currents flow in a body of a patient to achieve analgesia, cartilage repair and regeneration in the knee joint.

Abstract: A knee brace for continual electro-acupuncture stimulation system comprises: a first electrode configured to electrically coupled to acupuncture point Heting “(S 156)”; a second electrode configured to electrically coupled to acupuncture point “Spleen 10 ”; a third electrode configured to electrically coupled to acupuncture point “Stomach 34 ”; a fourth electrode configured to electrically coupled to acupuncture point “Hsiyen (S 145)”; a fifth electrode configured to electrically coupled to acupuncture point “Stomach 35 ”; a sixth electrode configured to electrically coupled to acupuncture point “Bladder 40 ”. The first, second, and third electrodes are connected to a polarity of voltage, and the fourth, fifth, and sixth electrodes are connected to an opposite polarity of voltage, such that electric currents flow in a body of a patient to achieve analgesia, cartilage repair and regeneration in the knee joint.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: The invention includes an electro-acupuncture stimulation system for in vivo and in situ analgesia and tissue repair and regeneration. Electrodes, which can be acupuncture needles, are percutaneously implanted that deliver a pulsed electrical current that creates an electrical field, which envelopes the targeted tissue and restores cell-generating homeostasis to the affected tissue and thereby promotes analgesia and tissue re-growth in otherwise debilitated or deteriorating tissue. Methods and apparatuses are also disclosed that may include a needle locking system and acupuncture-needle assemblies for long-term in situ electrical stimulation.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Abstract: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional memory arrays for higher storage density.

Abstract: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional memory arrays for higher storage density.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. The distal end may be provided with a cavity creation element, such as an inflatable balloon. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F2, and provides beneficial retention properties including immunity to disturbances. The vertical transistors are arranged in an alternating gate-facing orientation, with a common source formed on a first end and separate drains on their second ends. Word lines comprise alternating front gates and back gates shared by columns of gate-facing transistors on each side of it. The DGVC cell provides enhanced scalability allowing the continued scaling of DRAM technology and can be fabricated using low-cost semiconductor materials and existing fabrication techniques. Fabrication techniques and array biasing are also described for the DGVC cell arrays.

Abstract: A knee brace for continual electro-acupuncture stimulation system comprises: a first electrode configured to electrically coupled to acupuncture point “Heting (S 156)”; a second electrode configured to electrically coupled to acupuncture point “Spleen 10”; a third electrode configured to electrically coupled to acupuncture point “Stomach 34”; a fourth electrode configured to electrically coupled to acupuncture point “Hsiyen (S 145)”; a fifth electrode configured to electrically coupled to acupuncture point “Stomach 35”; a sixth electrode configured to electrically coupled to acupuncture point “Bladder 40”. The first, second, and third electrodes are connected to a polarity of voltage, and the fourth, fifth, and sixth electrodes are connected to an opposite polarity of voltage, such that electric currents flow in a body of a patient to achieve analgesia, cartilage repair and regeneration in the knee joint.

Abstract: A knee brace for continual electro-acupuncture stimulation system comprises a first circuit having a first circuit having a first electrode configured to electrically coupled to acupuncture point “Heting (S 156)” and a second electrode configured to electrically coupled to acupuncture point “Bladder 40”, a second circuit having a third electrode configured to electrically coupled to acupuncture point “Spleen 10” and a fourth electrode configured to electrically coupled to acupuncture point “Hsiyen (S 145)”, and a third circuit having a fifth electrode configured to electrically coupled to acupuncture point “Stomach 34” and a sixth electrode configured to electrically coupled to acupuncture point “Stomach 35”. The first, third, and fifth electrodes are connected to a polarity of voltage, and the second, fourth, and sixth electrodes are connected to an opposite polarity of voltage, such that electric currents flow in a body of a patient to achieve analgesia, cartilage repair and regeneration in the knee joint.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.