Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: A method and system for target detecting, editing and rebuilding by 3D image is provided, which comprises an inputting and picking unit, a training and detecting unit, a displaying and editing unit and a rebuilding unit. The inputting and picking unit receives a digital image and a LiDAR data and picks up a first parameter to form a 3D image. The training and detecting unit selects a target, picks up a second parameter therefrom, calculates the second parameter to generate a threshold and detects the target areas in the 3D image according to the threshold. The displaying and editing unit sets a quick selecting tool according to the threshold and edits the detecting result. The rebuilding unit sets a buffer area surrounding the target, picks up a third parameter therefrom and calculates the original shape of the target by the Surface Fitting method according to the third parameter.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. The distal end may be provided with a cavity creation element, such as an inflatable balloon. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced. Ridges on the corrugated substrate can be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.

Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: One embodiment of the invention comprises a differential composite in which bone cement everywhere or substantially everywhere contains at least some non-zero volume fraction of particles, and in which the local volume fraction of particles may vary from place to place in the composite in a controlled manner. The variation may be by identifiable region or may be in the form of a gradient of the local volume fraction of particles. In at least some places, the local volume fraction of particles may be such that the particles act as crack arrestors. Close to the interface with natural bone, the local volume fraction of particles may be greater. In at least some places adjoining natural bone, the local volume fraction of particles may be such as to allow bone ingrowth into appropriate region(s) of the composite, resulting in improved interfacial shear strength.

Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: The invention includes an electro-acupuncture stimulation system for in vivo and in situ analgesia and tissue repair and regeneration. Electrodes, which can be acupuncture needles, are percutaneously implanted that deliver a pulsed electrical current that creates an electrical field, which envelopes the targeted tissue and restores cell-generating homeostasis to the affected tissue and thereby promotes analgesia and tissue re-growth in otherwise debilitated or deteriorating tissue. Methods and apparatuses are also disclosed that may include a needle locking system and acupuncture-needle assemblies for long-term in situ electrical stimulation.

Abstract: An improved joint for a bicycle frame has a first sleeve for receiving a head tube and a second sleeve projecting laterally from the first sleeve, for receiving a top tube or a downtube, wherein the second sleeve includes an inner tube and an outer tube, which coaxially project from the first sleeve and which are spaced from each other with a circumferential clearance which is slightly larger than the thickness of the top tube or the downtube so that the top tube or downtube may be snap fit into this clearance.