Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced. Ridges on the corrugated substrate can be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. The distal end may be provided with a cavity creation element, such as an inflatable balloon. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F2, and provides beneficial retention properties including immunity to disturbances. The vertical transistors are arranged in an alternating gate-facing orientation, with a common source formed on a first end and separate drains on their second ends. Word lines comprise alternating front gates and back gates shared by columns of gate-facing transistors on each side of it. The DGVC cell provides enhanced scalability allowing the continued scaling of DRAM technology and can be fabricated using low-cost semiconductor materials and existing fabrication techniques. Fabrication techniques and array biasing are also described for the DGVC cell arrays.

Abstract: A method and system for target detecting, editing and rebuilding by 3D image is provided, which comprises an inputting and picking unit, a training and detecting unit, a displaying and editing unit and a rebuilding unit. The inputting and picking unit receives a digital image and a LiDAR data and picks up a first parameter to form a 3D image. The training and detecting unit selects a target, picks up a second parameter therefrom, calculates the second parameter to generate a threshold and detects the target areas in the 3D image according to the threshold. The displaying and editing unit sets a quick selecting tool according to the threshold and edits the detecting result. The rebuilding unit sets a buffer area surrounding the target, picks up a third parameter therefrom and calculates the original shape of the target by the Surface Fitting method according to the third parameter.

Abstract: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone cement injection needle is provided, having a laterally deflectable distal end. Systems are also disclosed, including the steerable injection needle, introducer and stylet. The system may additionally include a cement delivery gun, one-time use disposable cement cartridges and a cement mixing chamber. Methods are also disclosed.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. A multi step epitaxial process can be used to extend the ridges with different dopant types, high mobility semiconductor, and or advanced multi-layer strutures.

Abstract: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices.

Abstract: One embodiment of the invention comprises a differential composite in which bone cement everywhere or substantially everywhere contains at least some non-zero volume fraction of particles, and in which the local volume fraction of particles may vary from place to place in the composite in a controlled manner. The variation may be by identifiable region or may be in the form of a gradient of the local volume fraction of particles. In at least some places, the local volume fraction of particles may be such that the particles act as crack arrestors. Close to the interface with natural bone, the local volume fraction of particles may be greater. In at least some places adjoining natural bone, the local volume fraction of particles may be such as to allow bone ingrowth into appropriate region(s) of the composite, resulting in improved interfacial shear strength.

Abstract: The invention includes an electro-acupuncture stimulation system for in vivo and in situ analgesia and tissue repair and regeneration. Electrodes, which can be acupuncture needles, are percutaneously implanted that deliver a pulsed electrical current that creates an electrical field, which envelopes the targeted tissue and restores cell-generating homeostasis to the affected tissue and thereby promotes analgesia and tissue re-growth in otherwise debilitated or deteriorating tissue. Methods and apparatuses are also disclosed that may include a needle locking system and acupuncture-needle assemblies for long-term in situ electrical stimulation.

Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g.

Abstract: Methods and devices for augmenting bone, such as in performing vertebroplasty are disclosed. A bone implant with enhanced interfacial shear strength can include a container, such as a mesh bag, with a sidewall and an interior chamber portion. The sidewall can include an open-celled matrix and can be filled with a first media to promote bone ingrowth and enhanced interfacial shear strength. The interior chamber can be filled with a second media to prevent crack propagation. Delivery catheters with releasable coupling features to the implant are also disclosed.