Patents by Inventor Kinyip Phoa
Kinyip Phoa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908856Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.Type: GrantFiled: December 18, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Publication number: 20240055497Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
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Publication number: 20240038889Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Ayan KAR, Nicholas THOMSON, Benjamin ORR, Nathan JACK, Kalyan KOLLURU, Tahir GHANI
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Publication number: 20240006504Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: September 14, 2023Publication date: January 4, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI
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Patent number: 11837641Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Patent number: 11830818Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: GrantFiled: February 1, 2022Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11824116Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Ayan Kar, Nicholas Thomson, Benjamin Orr, Nathan Jack, Kalyan Kolluru, Tahir Ghani
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Patent number: 11799009Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.Type: GrantFiled: December 17, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani
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Patent number: 11737362Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.Type: GrantFiled: April 1, 2016Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11621334Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.Type: GrantFiled: January 29, 2019Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Said Rami, Hyung-Jin Lee, Surej Ravikumar, Kinyip Phoa
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Patent number: 11393934Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.Type: GrantFiled: December 27, 2017Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Ayan Kar, Kinyip Phoa, Justin S. Sandford, Junjun Wan, Akm A. Ahsan, Leif R. Paulson, Bernhard Sell
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Publication number: 20220157729Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Publication number: 20220068931Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Applicant: Intel CorporationInventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar
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Patent number: 11264329Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: GrantFiled: April 1, 2016Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11257822Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.Type: GrantFiled: November 21, 2019Date of Patent: February 22, 2022Assignee: Intel CorporationInventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar
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Publication number: 20210375926Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device according to some embodiments of the present disclosure includes a first nanoribbon of a first semiconductor material, and a second nanoribbon of a second semiconductor material, where the second nanoribbon is stacked above the first, thus forming a 3D structure. The device further includes a first transistor having a first source or drain (S/D) region and a second S/D region in the first nanoribbon, and a second transistor having a first S/D region and a second S/D region in the second nanoribbon. The first transistor may be configured to store a memory state of the memory cell, and the second transistor may be configured to control access to the memory cell, thus, together forming a nanoribbon-based 2T memory cell.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Applicant: Intel CorporationInventors: Rishabh Mehandru, Wilfred Gomes, Kinyip Phoa, Tahir Ghani
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Publication number: 20210335791Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Patent number: 11139300Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: GrantFiled: November 20, 2019Date of Patent: October 5, 2021Assignee: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Publication number: 20210272624Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.Type: ApplicationFiled: March 2, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani
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Patent number: 11087832Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.Type: GrantFiled: March 2, 2020Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani