Patents by Inventor Kiran Pangal

Kiran Pangal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cross-point memory single-selection write technique
    Patent number: 10056136
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal
  • Method and apparatus for multi-level setback read for three dimensional crosspoint memory
    Patent number: 10032508
    Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
  • Techniques to mitigate bias drift for a memory device
    Patent number: 10026460
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE
    Publication number: 20180196612
    Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 12, 2018
    Applicant: Intel Corporation
    Inventors: Kiran Pangal, Ravi J. Kumar
  • METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSIONAL CROSSPOINT MEMORY
    Publication number: 20180190353
    Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Balaji Srinivasan, Daniel Chu, Lark-Hoon Leem, John Gorman, Mase Taub, Sandeep Guliani, Kiran Pangal
  • MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
    Publication number: 20180182456
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 28, 2018
    Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
  • APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
    Publication number: 20180151206
    Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Reduced uncorrectable memory errors
    Patent number: 9934088
    Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
  • MANAGING DISTURBANCE INDUCED ERRORS
    Publication number: 20180068695
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 8, 2018
    Inventors: Prashant S. DAMLE, Frank T. HADY, Paul D. RUBY, Kiran PANGAL, Sowmiya JAYACHANDRAN
  • Methods and apparatuses for modulating threshold voltages of memory cells
    Patent number: 9905280
    Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Multistage set procedure for phase change memory
    Patent number: 9892785
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • Dynamic window to improve NAND endurance
    Patent number: 9857992
    Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Ravi J. Kumar
  • Transient current-protected threshold switching devices systems and methods
    Patent number: 9852789
    Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
  • Methods and apparatus to reduce threshold voltage drift
    Patent number: 9824767
    Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Feng Pan, Prashant S. Damle, Hanmant Pramod Belgal, Kiran Pangal
  • Phase change memory current
    Patent number: 9792986
    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
  • Managing disturbance induced errors
    Patent number: 9792963
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
    Publication number: 20170294228
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Application
    Filed: June 5, 2017
    Publication date: October 12, 2017
    Inventors: Mase J. TAUB, Sandeep K. GULIANI, Kiran PANGAL
  • TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
    Publication number: 20170287533
    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.
    Type: Application
    Filed: January 25, 2017
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J. Taub, Kiran Pangal
  • DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
    Publication number: 20170236580
    Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
  • CROSS POINT MEMORY CONTROL
    Publication number: 20170229172
    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
    Type: Application
    Filed: March 21, 2017
    Publication date: August 10, 2017
    Applicant: Intel Corporation
    Inventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI