Patents by Inventor Kiran Pangal

Kiran Pangal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9317364
    Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Publication number: 20160085621
    Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Applicant: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Patent number: 9286975
    Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Daniel J. Chu, Kiran Pangal, Nathan R. Franklin, Prashant S. Damle, Hu Chaohong
  • Patent number: 9268631
    Abstract: Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Lark-Hoon Leem, Kiran Pangal, Xin Guo
  • Publication number: 20160049209
    Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 18, 2016
    Inventors: Abhinav PANDEY, Hanmant P. BELGAL, Prashant S. DAMLE, Arjun KRIPANIDHI, Sebastian T. URIBE, Dany-Sebastien LY-GAGNON, Sanjay RANGAN, Kiran PANGAL
  • Patent number: 9257175
    Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 9, 2016
    Assignee: INTEL CORPORATION
    Inventors: Kiran Pangal, Raj K. Ramanujan, Robert W. Faber, Rajesh Sundaram
  • Patent number: 9250990
    Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Publication number: 20160012892
    Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 14, 2016
    Inventors: Nathan R. Franklin, Kiran Pangal
  • Patent number: 9231202
    Abstract: A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Max F. Hineman
  • Publication number: 20150380111
    Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Applicant: Intel Corporation
    Inventors: GAYATHRI RAO SUBBU, KIRAN PANGAL, NATHAN FRANKLIN
  • Patent number: 9224465
    Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Nathan R. Franklin, Sandeep K. Guliani, Mase J. Taub, Kiran Pangal
  • Patent number: 9208022
    Abstract: Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples, priorities may be adaptively assigned to entries included in the MRR table. The entries may be ordered for use based on the assigned priorities. In other examples, the MRR table may be ordered for use such that entries with a single MRR value for each read reference value may be used first over entries having multiple MRR values for each read reference value. For these other examples, the MRR table may be adaptively reordered based on which entries were successful or unsuccessful in recovering from a read error but may still be arranged to have single MRR value entries used first for use to recover from another read error.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 8, 2015
    Assignee: INTEL CORPORATION
    Inventors: Lark-Hoon Leem, Kiran Pangal, Xin Guo
  • Publication number: 20150348627
    Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Inventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
  • Patent number: 9202547
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Patent number: 9165647
    Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Sandeep Guliani, Kiran Pangal, Balaji Srinivasan, Chaohong Hu
  • Patent number: 9164836
    Abstract: Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: October 20, 2015
    Assignee: INTEL CORPORATION
    Inventors: Xin Guo, Kiran Pangal, Yogesh B. Wakchaure, Paul D. Ruby, Ravi J. Kumar
  • Patent number: 9153320
    Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Nathan R Franklin, Kiran Pangal
  • Publication number: 20150269994
    Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Applicant: Intel Corporation
    Inventors: NATHAN R. FRANKLIN, SANDEEP K. GULIANI, MASE J. TAUB, KIRAN PANGAL
  • Publication number: 20150262661
    Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: Intel Corporation
    Inventors: DANIEL J. CHU, KIRAN PANGAL, NATHAN R. FRANKLIN, PRASHANT S. DAMLE, HU CHAOHONG
  • Patent number: 9136873
    Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers