Patents by Inventor Kiran Pangal
Kiran Pangal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170221536Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Applicant: Micron Technology, Inc.Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
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Patent number: 9698830Abstract: Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed.Type: GrantFiled: February 28, 2013Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Ravi H. Motwani, Kiran Pangal
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Publication number: 20170186486Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: ApplicationFiled: October 24, 2016Publication date: June 29, 2017Applicant: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Patent number: 9685204Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.Type: GrantFiled: June 22, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Mase J Taub, Sandeep K. Guliani, Kiran Pangal
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Patent number: 9685213Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: November 9, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Publication number: 20170169886Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 9652321Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 23, 2014Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Ravi H. Motwani, Kiran Pangal
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Patent number: 9653127Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.Type: GrantFiled: December 15, 2015Date of Patent: May 16, 2017Assignee: Micron Technology, Inc.Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
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Patent number: 9619324Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 27, 2013Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Zion S. Kwok, Ravi H. Motwani, Kiran Pangal, Prashant S. Damle
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Patent number: 9613691Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.Type: GrantFiled: March 27, 2015Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Davide Mantegazza, Prashant S. Damle, Kiran Pangal, Hanmant P. Belgal, Abhinav Pandey
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Patent number: 9613698Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.Type: GrantFiled: May 13, 2016Date of Patent: April 4, 2017Assignee: INTEL CORPORATIONInventors: Davide Mantegazza, Kiran Pangal, Gerard H. Joyce, Prashant Damle, Derchang Kau, Davide Fugazza
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Patent number: 9601193Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 14, 2015Date of Patent: March 21, 2017Assignee: INTEL CORPORATIONInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20170076794Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Applicant: INTEL CORPORATIONInventors: RAYMOND W. ZENG, MASE J. TAUB, KIRAN PANGAL, SANDEEP K. GULIANI
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Patent number: 9589634Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.Type: GrantFiled: March 31, 2016Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Rakesh Jeyasingh, Nevil N. Gajera, Mase J Taub, Kiran Pangal
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Patent number: 9583187Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: March 28, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20170053698Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 9, 2016Publication date: February 23, 2017Inventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9543005Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.Type: GrantFiled: September 7, 2015Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Sandeep K Guliani, Kiran Pangal, Balaji Srinivasan, Chaohong Hu
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Patent number: 9543004Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.Type: GrantFiled: June 17, 2015Date of Patent: January 10, 2017Assignee: INTEL CORPORATIONInventors: Dany-Sebastien Ly-Gagnon, Kiran Pangal, Raymond W. Zeng, Mase J. Taub
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Patent number: 9543024Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.Type: GrantFiled: March 29, 2012Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Hiroyuki Sanda, Kiran Pangal, Xin Guo, Kaoru Naganuma
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Patent number: 9530523Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.Type: GrantFiled: June 25, 2014Date of Patent: December 27, 2016Assignee: Intel CorporationInventors: Gayathri Rao Subbu, Kiran Pangal, Nathan Franklin