Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta values. A target time for each of the one or more broken circuit paths may be adjusted.

Abstract: A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Abstract: Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

Abstract: Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

Abstract: Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

Abstract: Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

Abstract: A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Abstract: Embodiments of the invention are directed to a method and resulting structures for identifying an integrated circuit (IC) chip using optically-unique features. In a non-limiting embodiment of the invention, an imaging device generates an image of the chip. One or more optical features of the chip within the image can be determined and stored in a local or remote database. Metadata associated with the chip can be generated and linked with the one or more optical features of the chip and a unique identifier of the chip in the database.

Abstract: A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: After printing common features from a primary mask into a photoresist layer located over a substrate, a functional feature which is suitable for changing functionalities or the configurations of the common features according to a chip design is selected from a library of additional functional features in a secondary mask. The selected functional feature from the secondary mask is printed into the photoresist layer to modify the common features that already exist in the photoresist layer. The selection and printing of functional feature processes can be repeated until a final image corresponding to the chip design is obtained in the photoresist layer.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.