Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.

Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.

Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

Abstract: An integrated circuit (IC) can be configured to provide managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specified, managed voltage, through a VPI, to a set of circuits within a corresponding region of the IC.

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

Abstract: Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

Abstract: Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact.

Abstract: Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.