Abstract: Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.

Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

Abstract: According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.

Abstract: Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening.

Abstract: Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.

Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.

Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

Abstract: Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or an interposer (IP) can be used with existing equipment. Each control device can include a regulator, such as a latchable array of field effect transistors that can regulate power delivered to a respective package connector.

Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.

Abstract: A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.

Abstract: Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric.

Abstract: Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload conditions. In some embodiments, a computer implemented method includes obtaining survey data about at least one application workload for an integrated circuit (IC) corresponding to an IC design; generating latch state and clocking statistics about the IC design for the at least one application workload based upon the survey data; and determining a set of burn-in workload conditions for the IC design based upon the latch state and clocking statistics about the IC design.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

Abstract: An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.

Abstract: Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.