Abstract: A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silico

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silico

Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.

Abstract: An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.

Abstract: A process for improving the high voltage performances of a MOSFET transistor, and suppressing parasitic current induced snap-back behavior by placing a heavily doped P+ region around the grounded source. A first P+ region is placed adjacently to and in contact with the source and its metal lead, and a second P+ region may be placed under and in contact with the source and first P+ region, or form a layer under the entire transistor connected to the source by a P+ plug. Additional grounding of the source may be accomplished by a succession of alternating P+ region and N+ regions along the source edge.