Abstract: An apparatus for providing releasable attachment between a fiber connector and an opto-electronic assembly, the opto-electronic assembly utilizing an interposer substrate to support a plurality of opto-electronic components that generates optical output signals and receives optical input signals. An enclosure is used to cover the interposer substrate and includes a transparent region through which the optical output and input signals pass unimpeded. A magnetic connector component is attached to the lid and positioned to surround the transparent region, with a fiber connector for supporting one or more optical fibers magnetically attached to the connector component by virtue of a metallic component contained in the fiber connector. This arrangement provides releasable attachment of the fiber connector to the enclosure in a manner where the optical output and input signals align with the optical fibers in the connector.

Abstract: A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal.

Abstract: A process of producing N-acyl amino acid based surfactants of Formula I, wherein, R is selected from C6 to C22 alkyl group, R1 is selected from H, C1 to C4 alkyl, R2 is selected from all groups on ? carbon of natural amino acids, R3 is selected from COOX, CH2—SO3X, X is selected from Li+, Na+ or K+. The process comprising steps of: A) preparing fatty acid chlorides by halogenating fatty acids with either phosgene or thionyl chloride in the presence of catalytic amount of same or other N-acyl amino acid surfactant of Formula I or anhydrides of same surfactant; and B) reacting fatty acid chloride of step (A) with an amino acid in the presence of a base.

Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract: A process of producing N-acyl amino acid based surfactants of Formula I, wherein, R is selected from C6 to C22 alkyl group, R1 is selected from H, C1 to C4 alkyl, R2 is selected from all groups on ? carbon of natural amino acids, R3 is selected from COOX, CH2—SO3X, X is selected from Li+, Na+ or K+. The process comprising steps of: A) preparing fatty acid chlorides by halogenating fatty acids with either phosgene or thionyl chloride in the presence of catalytic amount of same or other N-acyl amino acid surfactant of Formula I or anhydrides of same surfactant; and B) reacting fatty acid chloride of step (A) with an amino acid in the presence of a base.

Abstract: An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices.

Abstract: An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.

Abstract: An interposer (support substrate) for an opto-electronic assembly is formed to include a thermally-isolated region where temperature-sensitive devices (such as, for example, laser diodes) may be positioned and operate independent of temperature fluctuations in other areas of the assembly. The thermal isolation is achieved by forming a boundary of dielectric material through the thickness of the interposer, the periphery of the dielectric defining the boundary between the thermally isolated region and the remainder of the assembly. A thermo-electric cooler can be used in conjunction with the temperature-sensitive device(s) to stabilize the operation of these devices.

Abstract: An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).

Abstract: An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner.

Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

Abstract: A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal.

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Abstract: An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).