Patents by Inventor Kishor A. Desai

Kishor A. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120126389
    Abstract: The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Kishor Desai, Belgacem Haba, Wael Zohni
  • Publication number: 20120104595
    Abstract: A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Belgacem Haba, Ilyas Mohammed, Ellis Chau, Sang Il Lee, Kishor Desai
  • Patent number: 7220753
    Abstract: Substituted pyrido[1,2-a]pyrazines of general formula I; wherein Ar and Ar1 represent various carbocyclic and heterocyclic aromatic rings; A represents O, S, SO, SO2, CHOH, C?O, or —(CR3R4); and n is 0–2, as well as precursors thereto, are ligands for dopamine receptor subtypes and serotonin (5HT) within the body and are therefore useful in the treatment of disorders of the dopamine and serotonin systems:
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: May 22, 2007
    Assignee: Pfizer Inc.
    Inventors: Kishor A. Desai, Anton F. Fliri, Mark A. Sanner
  • Publication number: 20060128072
    Abstract: A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.
    Type: Application
    Filed: December 13, 2004
    Publication date: June 15, 2006
    Inventors: Sarathy Rajagopalan, Kishor Desai, Shirish Shah
  • Patent number: 7041516
    Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: May 9, 2006
    Assignee: LSI Logic Corporation
    Inventors: Sarathy Rajagopalan, Kishor Desai, John P. McCormick, Maniam Alagaratnam
  • Publication number: 20050224955
    Abstract: A semiconductor package comprising a packaging substrate, a semiconductor die mounted with the substrate, a heatspreader, and a multi-layer heat transfer element arranged between the semiconductor die and the heat spreader to enable thermal communication between the die and the heat spreader is disclosed. The multi-layer heat transfer element includes a core spacer element sandwiched between a first layer of thermally conductive reflowable material and a second layer of thermally conductive reflowable material. Also disclosed are methods for forming such semiconductor packages and for forming multilayer heat transfer elements.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Inventors: Kishor Desai, Maniam Alagaratnam
  • Publication number: 20050060792
    Abstract: The article of clothing providing increased air circulation is a garment to which numerous panels are attached. In some embodiments the article of clothing is made from a wide gauge mesh material having modesty panels incorporated therein, or a liner beneath the mesh material. In other embodiments, the article of clothing is formed from a plurality of straps joined together to form a garment framework having first strips of hook and loop material attached to the outward facing surface of the straps, and a plurality of fabric panels having mating second strips of hook and loop material affixed to the peripheral border of the inward facing surface of the panels, so that panels can be added or removed as desired. In another embodiment, the article of clothing is formed from a garment body having strips of wide gauge mesh material defining openings in the garment at desired locations.
    Type: Application
    Filed: November 16, 2004
    Publication date: March 24, 2005
    Inventor: Kishor Desai
  • Patent number: 6858930
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: February 22, 2005
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai
  • Publication number: 20040239350
    Abstract: Probe cards for measuring package interconnect impedance. A first probe card includes a package having solder balls on a first surface, and an electrically conductive material on a second surface. The electrically conductive surface is configured to electrically contact bumps on the substrate. The solder balls are mountable to a test head inter phase board of the tester. The probe card does not have any probe pins, and is configured to make electrical contact with bumps on the substrate without using probe pins. A second probe card includes a substrate with solder balls on one side and solder on pad (SOP) on the other side. Vertical probe pins contact the SOP and act as an interface between a tester and solder bumps on a wafer.
    Type: Application
    Filed: October 23, 2003
    Publication date: December 2, 2004
    Inventors: Mohan R. Nagar, Kishor Desai, Shirish Shah
  • Publication number: 20040214830
    Abstract: Substituted pyrido[1,2-a]pyrazines of general formula I; wherein Ar and Ar1 represent various carbocyclic and heterocyclic aromatic rings; A represents O, S, SO, SO2, CHOH, C═O, or —(CR3R4); and n is 0-2, as well as precursors thereto, are ligands for dopamine receptor subtypes and serotonin (5HT) within the body and are therefore useful in the treatment of disorders of the dopamine and serotonin systems: 1
    Type: Application
    Filed: May 24, 2004
    Publication date: October 28, 2004
    Inventors: Kishor A. Desai, Anton F. Fliri, Mark A. Sanner
  • Patent number: 6777314
    Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: August 17, 2004
    Assignee: LSI Logic Corporation
    Inventors: Kishor Desai, John P. McCormick, Maniam Alagaratnam
  • Publication number: 20040072377
    Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 15, 2004
    Inventors: Sarathy Rajagopalan, Kishor Desai, John P. McCormick, Maniam Alagaratnam
  • Publication number: 20040065951
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Application
    Filed: August 11, 2003
    Publication date: April 8, 2004
    Applicant: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai
  • Publication number: 20040023481
    Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.
    Type: Application
    Filed: August 5, 2002
    Publication date: February 5, 2004
    Inventors: Kishor Desai, John P. McCormick, Maniam Alagaratnam
  • Patent number: 6680532
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: January 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai
  • Patent number: 6586825
    Abstract: A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: July 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Sarathy Rajagopalan, Kishor Desai, Maniam Alagaratnam
  • Publication number: 20030055061
    Abstract: Substituted pyrido[1,2-a]pyrazines of general formula I; wherein Ar and Ar1 represent various carbocyclic and heterocyclic aromatic rings; A represents O, S, SO, SO2, CHOH, C═O, or —(CR3R4); and n is 0-2, as well as precursors thereto, are ligands for dopamine receptor subtypes and serotonin (5HT) within the body and are therefore useful in the treatment of disorders of the dopamine and serotonin systems: 1
    Type: Application
    Filed: August 7, 2002
    Publication date: March 20, 2003
    Applicant: Pfizer Inc.
    Inventors: Kishor A. Desai, Anton F. Fliri, Mark A. Sanner
  • Patent number: 6525196
    Abstract: The present invention relates to compounds of formula 1, wherein R1, R2, R3 and R4 are defined as in the specification. These compounds are useful as psychotherapeutic agents.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: February 25, 2003
    Assignee: Pfizer Inc.
    Inventors: Gene M. Bright, Kishor A. Desai
  • Patent number: 6518161
    Abstract: A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: February 11, 2003
    Assignee: LSI Logic Corporation
    Inventors: Sarathy Rajagopalan, Kishor Desai
  • Publication number: 20020132811
    Abstract: Substituted pyrido[1,2-a]pyrazines of general formula I; wherein Ar and Ar1 represent various carbocyclic and heterocyclic aromatic rings; A represents O, S, SO, SO2, CHOH, C═O, or —(CR3R4); and n is 0-2, as well as precursors thereto, are ligands for dopamine receptor subtypes and serotonin (5HT) within the body and are therefore useful in the treatment of disorders of the dopamine and serotonin systems: 1
    Type: Application
    Filed: February 15, 2001
    Publication date: September 19, 2002
    Inventors: Kishor A. Desai, Anton F. Fliri, Mark A. Sanner