Patents by Inventor Kishore Kumar
Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250257843Abstract: The present invention relates to a platform for mounting devices. The platform comprises a frame made of one or more arms comprising through holes present near edges of the arms, and a plurality of support members configured to support the frame near the edges, each support member including a hollow shaft having internal threads passing via the through holes. The platform includes a plurality of spacers, each spacer being disposed on the through hole and comprising a bottom surface having a profile corresponding to a curvature of the frame, and a plurality of threaded plugs, each threaded plug passing through the spacer and the through hole. The threaded plug is secured with the internal threads of the hollow shaft positioned above the support member.Type: ApplicationFiled: April 25, 2023Publication date: August 14, 2025Inventors: Kishore Kumar AMPILI, R. BIJU
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Publication number: 20250259681Abstract: A memory device includes a memory array having memory cells associated with wordlines. Control logic, operatively coupled with the memory array, causes a first set of memory cells, associated with a first wordline of the memory array, to be programmed with a first set of threshold voltage distributions. After a second set of memory cells, associated with a second wordline that is adjacent to the first wordline, has been programmed, the control logic causes the first set of memory cells to be further coarse programmed with an intermediate third set of threshold voltage distributions that is greater in number than the first set of threshold voltage distributions. The control logic causes the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions.Type: ApplicationFiled: April 30, 2025Publication date: August 14, 2025Inventors: Huai-Yuan Tseng, Giovanni Maria Paolucci, Kishore Kumar Muchherla, James Fitzpatrick, Akira Goda
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Publication number: 20250246962Abstract: A stator bobbin includes a first winding support with an inner radial portion, an outer radial portion, and a winding space defined radially between the inner radial portion and the outer radial portion with respect to an axis of rotation. The winding space is configured to receive a plurality of windings of the e-machine. The inner radial portion and the outer radial portion extend along the axis between a first end of the stator bobbin and a second end of the stator bobbin. The stator bobbin further includes a winding retainer disposed at the first end and configured for receiving and retaining an end of the plurality of windings. Also, the stator bobbin includes a contoured flow surface disposed proximate the second end. The contoured flow surface defines a nonlinear flow path for a fluid coolant of the e-machine.Type: ApplicationFiled: March 14, 2024Publication date: July 31, 2025Applicant: Garrett Transportation I Inc.Inventors: Srinidhi Payyur Ramaswamy, Kishor Kumar K, Matej Kopecky, Praveen Kumar
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Publication number: 20250246964Abstract: A stator member for a directly-cooled e-machine includes a bobbin with a plurality of winding supports, a first isolator barrier member supported on a first angular side of a first winding support and a second isolator barrier member supported on a second angular side of the first winding support. The first and second isolator barrier members, the inner radial portion, and the outer radial portion cooperatively define an axial flow channel. The stator member further includes an end fluid deflector member that defines a redirection surface of the axial flow channel. The redirection surface is configured to redirect flow at the first axial end substantially from a first direction along the axis toward a second direction along the axis. The first direction is opposite the second direction.Type: ApplicationFiled: March 14, 2024Publication date: July 31, 2025Applicant: Garrett Transportation I Inc.Inventors: Srinidhi Payyur Ramaswamy, Kishor Kumar K, Praveen Kumar
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Publication number: 20250244898Abstract: A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a timer at initialization of a block family and stores a value of the timer before powering down the system while the block family is open. Upon the system powering up, the system determines a value of a data state metric associated with memory cells of the block family and estimates a time after program value of the memory cells based on the value of the data state metric. The processing device increments the value of the timer based on the time after program value and closes the block family based on the incremented value of the timer.Type: ApplicationFiled: March 20, 2025Publication date: July 31, 2025Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz, Kishore Kumar Muchherla
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Patent number: 12374132Abstract: Data processing systems for predicting one or more responses to a chemical substance based on biological images. At least some of the data processing systems include at least one processor configured to execute at least one artificial neural network trained to predict one or more responses to a chemical substance based on biological images. When the at least one processor is executing computer-executable instructions, the at least one processor is configured to carry out operations including processing spatially arranged image tile data through one or more data structures storing one or more portions of executable logic included in the artificial neural network to determine one or more responses of a patient to the chemical substance.Type: GrantFiled: February 4, 2021Date of Patent: July 29, 2025Assignee: SanofiInventors: Vardaan Kishore Kumar, Qi Tang
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Publication number: 20250231706Abstract: A set of data items programmed to a first region of a memory subsystem according to a first sequence is identified. The first sequence does not correspond to a target sequence. The set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.Type: ApplicationFiled: April 1, 2025Publication date: July 17, 2025Inventors: Karl David Schuh, Kishore Kumar Muchherla, Daniel Jerre Hubbard, James Fitzpatrick
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Patent number: 12357578Abstract: The invention relates to a solid, pharmaceutical composition in compressed tablet form. The tablet comprises an ibuprofen core tablet, a pair of protective barriers and a famotidine outermost coating. The ibuprofen core tablet comprises ibuprofen and one or more pharmaceutically acceptable excipients selected from disintegrants, diluents, fillers, binders, glidants and lubricants. The pair of protective barrier coatings surround the ibuprofen core tablet. The first coating comprises a methacrylic acid and ethyl acrylate copolymer, a surfactant, and hydroxypropylmethylcellulose. The second coating comprises hydroxypropylmethylcellulose, and a plasticizer. The outermost coating comprises famotidine, polyvinyl alcohol and a plasticizer.Type: GrantFiled: October 8, 2021Date of Patent: July 15, 2025Assignee: APPCO PHARMA LLCInventors: Peddanna Gumudavelli, Kishore Kumar Konda, Srinivasa R. Paruchuri, M. V. K. Satish, Y. V. Raghava Chowdary
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Patent number: 12340126Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.Type: GrantFiled: April 1, 2024Date of Patent: June 24, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
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Publication number: 20250201316Abstract: An example memory device includes a memory array and processing logic, operatively coupled with the memory array. The processing logic is configured to perform operations, including: identifying a set of sample voltages associated with a chosen read level; obtaining, for each sample voltage of the set of sample voltages, a cell count corresponding to a number of target cells of the memory array that have a threshold voltage lower than the sample voltage; and determining, based on the cell count, a calibrated read level associated with a state information bin to which the target cells are assigned.Type: ApplicationFiled: February 26, 2025Publication date: June 19, 2025Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
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Patent number: 12335862Abstract: A mobile computing device comprising: a wireless communications interface configured to connect to a network deployed by a plurality of access points; a short-range wireless communications interface configured to communicate with one or more nearby computing devices; a processor interconnected with the wireless communications interface and the short-range wireless communications interface, the processor configured to: obtain, from the one or more nearby computing devices via the short-range wireless communications interface, a list of potential access points, wherein each potential access point comprises one of the plurality of access points by which a respective nearby computing device is connected to the network; select one of the potential access points as a target access point, wherein the target access point is different from a home access point to which the wireless communications interface is currently connected; and control the wireless communications interface to roam to the selected target access poType: GrantFiled: August 5, 2022Date of Patent: June 17, 2025Assignee: Zebra Technologies CorporationInventors: Darpan Majumder, Venkata Aneel Kumar Inuganti, Mahesh Kumar Edar, Surya Kantha Rao Kandoti, Chiranjeevi Kamakshipalya Hanumanthaiah, Naga Babu Parsi, Kishore Kumar Pathankanur, Mahendiran Balasubramaniyam, HariPrasad Mosuru Chandrasekhar, Phanindra Kumar Gollapudi, Punith Gangadhara
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Patent number: 12334153Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.Type: GrantFiled: September 9, 2022Date of Patent: June 17, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
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Patent number: 12334142Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.Type: GrantFiled: July 29, 2022Date of Patent: June 17, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Violante Moschiano, Akira Goda, Jeffrey S. McNeil, Eric N. Lee
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Patent number: 12333398Abstract: A method comprises receiving configuration data comprising a plurality of parameters of at least one computing environment. One or more of the parameters correspond to integration of one or more elements of the least one computing environment with one or more other elements at least one of within and external to the least one computing environment. In the method, the parameters are analyzed to detect one or more anomalies in the configuration data, and the configuration data and the one or more detected anomalies are inputted to one or more machine learning models. The method also comprises determining, using the one or more machine learning models, one or more modifications to at least one of the plurality of parameters based on the inputted configuration data and one or more detected anomalies, and transmitting the determination comprising the one or more modifications to a user over a communications network.Type: GrantFiled: September 18, 2020Date of Patent: June 17, 2025Assignee: Dell Products L.P.Inventors: Navin Kumar Neithalath, Navnit Varu, Venkata Kishore Kumar Reddy Chintham, Bijan Kumar Mohanty, Hung Dinh
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Patent number: 12332742Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.Type: GrantFiled: February 5, 2024Date of Patent: June 17, 2025Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Patrick Khayat, Sampath Ratnam, Kishore Kumar Muchherla, Jiangang Wu, James Fitzpatrick
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Publication number: 20250187073Abstract: The present disclosure is directed, in certain embodiments, a component of a mechanical apparatus. The component includes a cast body with an initial structure formed by a mold and at least one feature deposited on the cast body using a solid state additive manufacturing process, such that in combination the initial structure and the at least one feature form a complete structure of the component.Type: ApplicationFiled: December 11, 2023Publication date: June 12, 2025Inventors: Ryan Patry, Kishore Kumar Tenneti, William Paul Fallon, JR., Nathaniel Ferguson Dew
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Patent number: 12326782Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.Type: GrantFiled: March 20, 2024Date of Patent: June 10, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Niccolo' Righetti, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, James Fitzpatrick, Ugo Russo
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Patent number: 12327048Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.Type: GrantFiled: December 29, 2023Date of Patent: June 10, 2025Assignee: Micron Technology, Inc.Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Patrick R. Khayat, Sundararajan Sankaranarayanan, Jeremy Binfet, Akira Goda
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Publication number: 20250182810Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.Type: ApplicationFiled: February 7, 2025Publication date: June 5, 2025Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
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Publication number: 20250181259Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family associated with a specified memory address; identify a first threshold voltage offset bin associated with the first block family; calibrate a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family, associating the first block family with a second threshold voltage offset bin; and read, using the second threshold voltage offset bin, data from the specified memory address.Type: ApplicationFiled: February 3, 2025Publication date: June 5, 2025Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz