Patents by Inventor Kishore Kumar
Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147686Abstract: An example system includes a memory device; and a processing device, operatively coupled to the memory device, to perform operations, including: programming a plurality of pages of the memory device; adjusting a program verify voltage associated with the plurality of pages; responsive to determining that a first error rate of a first page of the plurality of pages exceeds a second error rate of a second page of the plurality of pages, performing a recovery operation on the first page to produce recovered data; and storing the recovered data on the memory device.Type: ApplicationFiled: January 13, 2025Publication date: May 8, 2025Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
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Patent number: 12293099Abstract: A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.Type: GrantFiled: January 18, 2023Date of Patent: May 6, 2025Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz, Kishore Kumar Muchherla
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Publication number: 20250140317Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.Type: ApplicationFiled: January 2, 2025Publication date: May 1, 2025Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
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Publication number: 20250130736Abstract: A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.Type: ApplicationFiled: September 30, 2024Publication date: April 24, 2025Inventors: Kishore Kumar Muchherla, Akira Goda, Huai-Yuan Tseng, David Scott Ebsen
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Publication number: 20250111073Abstract: The present embodiments relate to systems and methods to selectively encrypt data for a generative artificial intelligence (GenAI) application. The systems and methods as described herein provide access control for generative AI applications by applying encryption at the data level for all sensitive and regulated data values. Each data value identified as containing sensitive data can be individually encrypted with associated metadata that supports downstream processing by generative AI components and for access control. The encryption can be performed by inline network proxies that are configured by a centralized configuration management service. The use of centralized configuration management can be used for encryption and associated access control policies that is consistent across all of the data paths into and out of the protected systems.Type: ApplicationFiled: November 18, 2024Publication date: April 3, 2025Inventors: Min-Hank Ho, Palanivel Rajan Shanmugavelayutham, Kishore Kumar Chandrasekaran, Balaji Govindan, Priyadarshan Kolte
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Publication number: 20250111937Abstract: Techniques disclosed herein provide a layered healthcare medical stack for embodying the architecture of a subject-centric smart hospital (SH) with customizable smart services. A subject centric matrix hosted on a centralized cloud that is configured to provide interoperability, integration, and customization of services for various healthcare organizations. Data is obtained for each subject to create a subject-specific persona for performing prescriptive and predictive analysis thereby generating alerts and trends based on the current and historical healthcare data of a subject. The subject-centric matrix can enable healthcare facilities to choose any service in any layer without a prerequisite service to be in place first.Type: ApplicationFiled: July 5, 2024Publication date: April 3, 2025Applicant: Cerner Innovation, Inc.Inventors: Praveen Bhat Gurpur, Ranjani Rajagopalan, Priyanka Verma, Suchitra Joyce Phillips, Kishore Kumar Naik Pujari, Ankur Chatter, Amarrtya Jana, Harish Raghupatruni, Praveen Kumar Patil
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Publication number: 20250112768Abstract: A method and system for protecting sensitive data in a generative AI system is disclosed. The method includes encrypting sensitive data fields at a field level using a first encryption proxy in a data store, labeling the encrypted data fields with metadata in the data store, interfacing the data store to the generative AI system, receiving a user prompt at a second proxy, sending the user prompt to the generative AI system, generating a response by the generative AI system, receiving the response from the generative AI system, and selectively decrypting, by the second proxy, sensitive data in the response based on user authorization. In some embodiments, the metadata comprises encryption keys information and access control policies.Type: ApplicationFiled: September 26, 2024Publication date: April 3, 2025Inventors: Min-Hank Ho, Priyadarshan Kolte, Palanivel Rajan Shanmugavelayutham, Kishore Kumar Chandrasekaran, Balaji Govindan
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Patent number: 12266407Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.Type: GrantFiled: April 18, 2023Date of Patent: April 1, 2025Assignee: Micron Technology, Inc.Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
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Patent number: 12249364Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.Type: GrantFiled: August 17, 2022Date of Patent: March 11, 2025Assignee: Micron Technology, Inc.Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
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Publication number: 20250077416Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.Type: ApplicationFiled: July 23, 2024Publication date: March 6, 2025Inventors: Huai-Yuan Tseng, Xiangyu Tang, Eric N. Lee, Haibo Li, Kishore Kumar Muchherla, Akira Goda
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Publication number: 20250078932Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.Type: ApplicationFiled: November 20, 2024Publication date: March 6, 2025Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sead Zildzic, Akira Goda, Jonathan S. Parry, Violante Moschiano
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Publication number: 20250058523Abstract: Automated multi-layer two-dimensional printing is provided via a plurality of supply tanks; a deposition tank; a plurality of pumps each comprising: a pipeline in fluid communication with one supply tank and the deposition tank on opposing ends; a bearing holder, including a plurality of rotatable bearings arranged at a shared angle to each other relative to an axis of rotation for the bearing holder; a housing wall, wherein at least a subset of the plurality of rotatable bearings compresses the pipeline against the housing wall; and a motor configured to rotate the bearing holder about the axis of rotation and push a fluid through the pipeline by moving the plurality of rotatable bearings about the axis of rotation to change where the rotatable bearings compress the pipeline against the housing wall; and a spray deposition nozzle in fluid communication with the deposition tank.Type: ApplicationFiled: December 20, 2022Publication date: February 20, 2025Inventors: Kishor Kumar Sadasivuni, Muni Raj Maurya, Mohammad Talal Houkan, John-John Cabibihan
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Patent number: 12229000Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.Type: GrantFiled: June 8, 2023Date of Patent: February 18, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy, Devin M. Batutis, Xiangang Luo
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Publication number: 20250053301Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Inventors: Jeffrey S. McNeil, Jonathan S. Parry, Ugo Russo, Akira Goda, Kishore Kumar Muchherla, Violante Moschiano, Niccolo' Righetti, Silvia Beltrami
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Publication number: 20250052816Abstract: A method and system for monitoring an insulation resistance (IR) of an e-machine includes a bridge circuit arrangement. A voltage across the bridge circuit arrangement is detected. The IR is calculated as a resistance in the bridge circuit arrangement associated with the detected voltage.Type: ApplicationFiled: December 8, 2023Publication date: February 13, 2025Applicant: Garrett Transportation I Inc.Inventors: Poomkuzhimannil John, Abhijith Vikraman Pillai Santhamma, Kishor Kumar K
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Patent number: 12216573Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: GrantFiled: December 22, 2023Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Patent number: 12217799Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.Type: GrantFiled: March 10, 2023Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
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Patent number: 12210994Abstract: Aspects of the present disclosure provide systems, methods, and computer-readable storage media that support application portfolio management. Input data may be received that is associated with a set of applications. The input data may indicate, for each application of the set of applications, a name of the application and a description of the application. For an application of the set of applications, a functional score, a cost, and a technical score may be determined based on the name of the application, the description of the application, or a combination thereof. A disposition recommendation for the application may be determined based on the functional score, the cost, and the technical score. In some implementation, an indication of the disposition recommendation of the application may be output via a graphical user interface.Type: GrantFiled: August 30, 2022Date of Patent: January 28, 2025Assignee: Accenture Global Solutions LimitedInventors: Sandeep Bharihoke, Kishore Kumar Sampath, Akshaya Purushothama Kadidal, Logesh Subramani, Barun Prakash Nanda, Shiv Chhabra, Ganesan Ramachandran, Andrew Lanktree, Neeraj Arora
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Publication number: 20250028447Abstract: A memory device includes an array of memory cells associated with a plurality of wordlines and control logic operatively coupled with the array of memory cells. The control logic can receive a program command comprising a digital value indicating that a physical address of the program command corresponds to a retired wordline of the plurality of wordlines. The control logic can generate dummy data in response to detecting the digital value within the program command. The memory logic can cause the dummy data to be programmed to memory cells that are selectively coupled to the retired wordline.Type: ApplicationFiled: October 4, 2024Publication date: January 23, 2025Inventors: Jeremy Binfet, Violante Moschiano, James Fitzpatrick, Kishore Kumar Muccherla, Jeffrey S. McNeil, Phong Sy Nguyen
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Publication number: 20250029641Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.Type: ApplicationFiled: October 9, 2024Publication date: January 23, 2025Applicant: MICRON TECHNOLOGY, INC.Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. MCNeil, Jung-Sheng Hoei