Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Abstract: Aspects of the present disclosure provide systems, methods, and computer-readable storage media that support application portfolio management. Input data may be received that is associated with a set of applications. The input data may indicate, for each application of the set of applications, a name of the application and a description of the application. For an application of the set of applications, a functional score, a cost, and a technical score may be determined based on the name of the application, the description of the application, or a combination thereof. A disposition recommendation for the application may be determined based on the functional score, the cost, and the technical score. In some implementation, an indication of the disposition recommendation of the application may be output via a graphical user interface.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

Abstract: A memory device includes an array of memory cells associated with a plurality of wordlines and control logic operatively coupled with the array of memory cells. The control logic can receive a program command comprising a digital value indicating that a physical address of the program command corresponds to a retired wordline of the plurality of wordlines. The control logic can generate dummy data in response to detecting the digital value within the program command. The memory logic can cause the dummy data to be programmed to memory cells that are selectively coupled to the retired wordline.

Abstract: Methods of processing a substrate in a PVD chamber are provided herein. In some embodiments, a method of processing a substrate in a PVD chamber, includes: sputtering material from a target disposed in the PVD chamber and onto a substrate, wherein at least some of the material sputtered from the target is guided to the substrate through a magnetic field provided by one or more upper magnets disposed about a processing volume of the PVD chamber above a support pedestal for the substrate in the PVD chamber, one or more first magnets disposed about the support pedestal and providing an increased magnetic field strength at an edge region of the substrate, and one or more second magnets disposed below the support pedestal that increase a magnetic field strength at a central region of the substrate.

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

Abstract: A computing system (100) that includes at least one microapp (202) and a container application (204) configured to receive an application output from the microapp(s) (202,602) via an application programming interface. The computing system (100) can include at least one processor (112,132) and at least one tangible, non-transitory computer-readable medium that stores instructions that, when executed by the at least one processor (112,132), cause the at least one processor (112,132) to perform operations. The operations can include providing, for display within a first panel (304) in a user interface (306), a navigation bar (302) based on data received from the container application (204); receiving, at the container application (204), the application output from the at least one microapp (202) via the application programming interface; and providing, for display within a second panel in the user interface (306), data describing the application output.

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: A method in a computing device includes: establishing an association with an base station; in response to establishing the association, transmitting one or more unencrypted messages to the base station using one or more data rates selected according to an optimization sequence; receiving, from the base station, one or more acknowledgements to the one or more unencrypted messages; based on the one or more acknowledgements, selecting an active data rate; and sending encrypted data to the base station using the active data rate.

Abstract: An apparatus having memory cells, an error correction module with a predetermined code rate, a processing device configured to arrange data storage in the memory cells for improved capability in recovering from random bit errors in raw data retrieved from the memory cells. For example, user data and redundant data are stored in the memory cells. The redundant data is generated according to the predetermined code rate from not only the user data but also known data. The known data is not stored in the memory cells. As a result, the error correction module has increased capability in recovering from random bit errors in raw data retrieved from the memory cells. The increased capability can be used to extend the useful life of the memory cells and/or improve the reliability of retrieving error free data from the memory cells.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.