Abstract: A static random access memory comprising a memory cell array, a plurality of peripheral circuits, first and second power-supply voltage lines, a bonding pad, and a level-shifting circuit. The array has static memory cells each having resistors functioning as load elements. The peripheral circuits control the writing of data into, and the reading of data from, the static memory cells. The first power-supply voltage line applies a first power-supply voltage to the peripheral circuits. The bonding pad is connected to the first power-supply voltage line. The second power-supply voltage line applies a second power-supply voltage to the static memory cells. The level-shifting means is connected between the first and second power-supply voltage lines, for shifting the level of the first power-supply voltage and applying the level-shifted voltage to the static memory cells via said second power-supply voltage line.

Abstract: A semiconductor device which comprises an N channel MOS transistor deposited on a P conductivity substrate, a P channel MOS transistor mounted on said N channel MOS transistor, and a high melting metal layer interposed between the drain regions of said first and second MOS transistors in a direction perpendicular to the surface of said semiconductor device to thereby effect ohmic contact between said drain regions.

Abstract: A semiconductor memory device includes memory cells arranged in a matrix array, a plurality of pairs of bit lines, each pair of bit lines being connected to the memory cells on the same column, a plurality of pairs of switching MOS transistors, each pair of MOS transistors being connected between a power source terminal and each pair of bit lines, and a precharge control circuit for supplying a control signal to the gates of the switching MOS transistors. This memory device further includes delay circuits connected in series with each other, and the delay circuits delay the control signal from the precharge control circuit and supply the control signal to the gates of the switching MOS transistors at different timings.

Abstract: A logic circuit comprises at least one signal input terminal, an output terminal, an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, to discharge the output terminal, and an MOS type logic circuit for supplying to the base of the first bipolar transistor a signal of a level corresponding to an input signal supplied to the at least one signal input terminal. The logic circuit further comprises a control MOS transistor coupled between a power source terminal and the base of the bipolar transistor, for supplying part of the base current to the bipolar transistor in response to a signal at the output terminal.

Abstract: The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film.

Abstract: A transistor circuit with hysteresis operation, which is formed with a detector part and selector part. The detector part detects a change in the level of an input signal according to one of first and second threshold levels, and generates an output signal having a level corresponding to the input signal. The level of the input signal is changed between a first level and a second level which is lower than the first level. The first and second threshold levels fall within a range defined between the first and second levels. The selector part selects one of the first and second threshold levels in accordance with the level of the output signal, and applies the selected one threshold level to the detector part.

Abstract: A method of manufacturing a semiconductor device has the steps of forming at least one groove in a semiconductor substrate having at least one well in a surface region thereof, forming an insulating film on the overall surface of the semiconductor substrate including an inner surface of the groove, selectively etching the insulating film so as to leave the insulating film in the groove, and burying a conductive material in the groove whose inner surface is covered with the remaining insulating film so as to form a conductive layer which is connected to at least one member selected from the group consisting of the well and the semiconductor substrate, and to a power supply.

Abstract: A semiconductor memory device is comprised of: a semiconductor memory having a plurality of memory cells arrayed in a matrix, a memory area of the memory including a main memory section and an auxiliary memory section; a plurality of row lines for selecting the memory cells connected to the memory cells; a plurality of power source lines provided corresponding to the row lines; and a circuit for separating or disconnecting from a power source the power source lines connected to the memory cells in an unused memory area of the semiconductor memory.

Abstract: A sense amplifier in use for a memory device is made up of a pair of Schmitt trigger circuits. These Schmitt trigger circuits are cross coupled with each other so that each of the Schmitt trigger circuits operates in response to a predetermined high potential difference. The predetermined potential difference is high enough to operate each Schmitt trigger circuit according to the steeper slope of the two long slopes of a hysteresis loop of the Schmitt trigger circuit.

Abstract: A static type memory circuit has a plurality of memory cells arranged in a matrix form, a plurality of word lines and a plurality of pairs of bit lines, each of the word lines being coupled to memory cells on a corresponding row, each pair of the bit lines being commonly coupled to memory cells on a corresponding column, a sense amplifier circuit coupled to the bit lines, a row decoder for energizing one of the word lines in response to row address data, a transition detecting circuit for generating an output signal when the row address data is changed, a control signal generator for causing the sense amplifier circuit to be active in response to the output signal from the transition detecting circuit, and a precharge control circuit for controlling precharging of the bit lines in response to the output signal from the transition detecting circuit.

Abstract: An output buffer circuit has a data input terminal which receives logic data, load and drive transistors, a driver for selectively turning on the transistors in accordance with the logic value of the logic data, a data output terminal which is connected to a power source terminal of the VDD level through a current path of the load transistor and is grounded through a current path of the drive transistor, and a capacitor connected as a load to the data output terminal. The output buffer circuit further has a transistion detector circuit for generating a pulse signal in response to a change in level of each of address signals, and a preset circuit for supplying, in response to the pulse signal, a charge or discharge current to the capacitor while a voltage at the data output terminal is not at the VDD/2 level.

Abstract: A semiconductor memory device includes a plurality of bit memory sections, a plurality of column select circuits for selecting columns of each of the bit memory sections, and a spare memory section containing a column of spare memory cells. The first switching circuits are coupled with the column select circuits and a second switching circuit is coupled with the spare memory section. A control circuit responds to a specific address by turning off the selected one of the first switching circuits and turning on the second switching circuit.

Abstract: A programming circuit used with a semiconductor memory comprising normal as well as spare memory cells allows any of the normal memory cells to be replaced by a spare memory cell and includes a fuse and a MOSFET connected in series between first and second power supply terminals. A voltage signal at the junction between the fuse and the MOSFET is delivered to the gate of the MOSFET after being delayed after power is supplied.

Abstract: A positive feedback amplifier circuit for possible use with a semiconductor memory device includes first and second MOS transistors whose current paths are connected together between two power source terminals, the gate of the first MOS transistor being connected to a clock. A third MOS transistor has a current path connected between one of the power source terminals and the gate of the second MOS transistor and also has a gate connected to the junction between the first and second MOS transistors and to a resistive means whose other end is connected to one of the power source terminals.

Abstract: Bit line precharge circuits, sense AMP circuits and input-output line precharge circuits are respectively divided into two groups by select circuits which are controlled by a select control signal. Only the selected precharge circuits and the sense AMP circuits are enabled before a readout operation. The peak current for precharging bit lines is reduced to one-half as compared to conventional circuits due to the decrease of stray capacitance to be precharged.

Abstract: There is provided a signal propagating device for receiving an input signal at an input end thereof and supplying the input signal to a plurality of memory cells arranged in one row. The signal propagating device includes a word line connected to transmit the input signal and having a plurality of line segments electrically coupled to the memory cells. A preceding one of the line segments is formed to have a larger average width than a succeeding one of the line segments.

Abstract: A semiconductor memory device is provided, including a plurality of MOS memory cells arranged in a matrix fashion, word lines for selectively transferring an access signal to the MOS memory cells, plural pairs of data lines for effecting data transfer with resepct to the MOS memory cells, sense amplifiers connected to the plural pairs of data lines to amplify data signals on the data lines, and a clock pulse generator connected to produce a clock pulse for activating the sense amplifiers. The memory device further includes a dummy word line arranged in the same manner as the word lines, and a dummy decoder connected to energize the clock pulse generator through the dummy word line so that the clock pulse generator produces a clock pulse to activate the sense amplifiers for preset period of time.

Abstract: A semiconductor memory device which comprises data lines each connected with memory cells, a precharging circuit for precharging the data lines, and an address signal state transition detector to detect a state transition of an address signal to cause the precharging circuit to precharge the data lines. The semiconductor memory device further comprises a data line voltage level detect circuit for detecting the voltage level of the data lines being precharged to minimize the precharging period of data lines, and a flip-flop circuit which causes the precharging circuit to precharge the data lines when an address signal state transition is detected by the address signal state transition detector, and which disables the precharging circuit from precharging the data lines when it is detected by the voltage level detect circuit that the data lines have been precharged to a predetermined voltage level.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a matrix fashion, word lines each connected commonly to the memory cells arranged on the same row, plural pairs of data lines each pair connected commonly to the memory cells on the same column line, and a row decoder connected to the word lines. The semiconductor memory device further includes positive feedback amplifiers connected to the work lines, which respond to voltages on the word lines at a preset or higher level to pull up the potential on the word lines to a higher level.

Abstract: A voltage sense circuit in which first and second parallel connections of complementary MOS transistors are connected between a pair of signal lines connected to memory cells and outputs of a flip-flop circuit for detecting a potential change of the signal line caused by data readout from an accessed memory cell. MOS transistors of one channel type in the parallel connections are adapted to precharge output node capacitors of the flip-flop circuit to a supply voltage level, while MOS transistors of the other channel type are adapted to couple complementary output voltage levels of the flip-flop circuit produced after the data readout and operation of the flip-flop circuit to the signal lines. Use of the parallel connections of complementary MOS transistors enables the application of a single power source for producing gate signals of these MOS transistors.