Patents by Inventor Kiyohiro Furutani
Kiyohiro Furutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8462560Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).Type: GrantFiled: February 1, 2010Date of Patent: June 11, 2013Assignee: Elpida Memory, Inc.Inventors: Kiyohiro Furutani, Seiji Narui
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Patent number: 8362827Abstract: A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.Type: GrantFiled: January 13, 2010Date of Patent: January 29, 2013Assignee: Elpida Memory, Inc.Inventors: Kenji Takahashi, Kiyohiro Furutani
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Publication number: 20120275256Abstract: A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active command and supply, as the power voltage, the power line with a first voltage during a first period and a second voltage lower than the first voltage during a second period. The control circuit is further configured to respond to a refresh command and supply, as the power voltage, the power line with the second voltage during both the first and second periods.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Kiyohiro FURUTANI, Takuya KADOWAKI
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Patent number: 8300480Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.Type: GrantFiled: October 4, 2010Date of Patent: October 30, 2012Assignee: Elpida Memory, Inc.Inventor: Kiyohiro Furutani
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Publication number: 20120263004Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.Type: ApplicationFiled: June 25, 2012Publication date: October 18, 2012Applicant: Elpida Memory Inc.Inventor: Kiyohiro Furutani
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Patent number: 8248879Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.Type: GrantFiled: December 10, 2009Date of Patent: August 21, 2012Assignee: Elpida Memory, Inc.Inventor: Kiyohiro Furutani
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Publication number: 20120033506Abstract: A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.Type: ApplicationFiled: August 5, 2011Publication date: February 9, 2012Inventors: Kiyohiro Furutani, Yoshinori Matsui
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Patent number: 7940112Abstract: To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.Type: GrantFiled: April 2, 2010Date of Patent: May 10, 2011Assignee: Elpida Memory, Inc.Inventors: Shinya Okuno, Kiyohiro Furutani
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Publication number: 20110080797Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.Type: ApplicationFiled: October 4, 2010Publication date: April 7, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Kiyohiro Furutani
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Patent number: 7885132Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: May 7, 2009Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Publication number: 20100253317Abstract: To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.Type: ApplicationFiled: April 2, 2010Publication date: October 7, 2010Applicant: Elpida Memory, Inc.Inventors: Shinya OKUNO, Kiyohiro FURUTANI
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Publication number: 20100195412Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized(FIG. 2).Type: ApplicationFiled: February 1, 2010Publication date: August 5, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Kiyohiro FURUTANI, Seiji NARUI
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Publication number: 20100191987Abstract: To provide a first internal voltage generating circuit that generates an internal voltage based on a first external voltage and a second internal voltage generating circuit that generates the internal voltage based on a second external voltage. The semiconductor device generates an internal voltage from a plurality of the first and second external voltages. These external voltages can be utilized efficiently depending on a load state. Therefore, even in a semiconductor device with greatly varying consumption power, it is not necessary to enlarge only a particular power supply device.Type: ApplicationFiled: January 28, 2010Publication date: July 29, 2010Applicant: Elpida Memory, Inc.Inventors: Kiyohiro Furutani, Shoji Kaneko
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Publication number: 20100181839Abstract: A semiconductor device includes two functional circuits, PMOS transistors and NMOS transistors. The PMOS transistors control whether or not a power supply potential is to be delivered to functional circuits, and the NMOS transistors control whether or not a power supply potential GND is to be delivered to the functional circuits. An external terminal supplied with a third power supply potential and another external terminal is supplied with a fourth power supply potential higher than the third power supply potential. A power supply control circuit delivers a control signal, having the fourth power supply potential as amplitude, to transistors to control the electrically conducting state or the electrically non-conducting state of transistors. The power supply control circuit also delivers a control signal, having the third power supply potential as amplitude, to transistors to control the electrically conducting or non-conducting state of the NMOS transistors.Type: ApplicationFiled: January 13, 2010Publication date: July 22, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Kenji Takahashi, Kiyohiro Furutani
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Publication number: 20100157713Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.Type: ApplicationFiled: December 10, 2009Publication date: June 24, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Kiyohiro Furutani
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Publication number: 20090238022Abstract: A semiconductor device includes: a setting circuit which sets a first setting value; a control circuit which receives a predetermined control signal and the first setting value so as to output a second setting value; and an output circuit which outputs a predetermined level in response to the first setting value or the second setting value, wherein the second setting value is changed from the first setting value based on the predetermined control signal.Type: ApplicationFiled: March 24, 2009Publication date: September 24, 2009Inventor: Kiyohiro FURUTANI
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Publication number: 20090213667Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: ApplicationFiled: May 7, 2009Publication date: August 27, 2009Applicant: Renesas Technology CorporationInventors: Takashi KUBO, Takashi ITOH, Yasuhiro KASHIWAZAKI, Taku OGURA, Kiyohiro FURUTANI
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Patent number: 7542363Abstract: An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition.Type: GrantFiled: March 18, 2005Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Takashi Kubo, Takashi Itoh, Yasuhiro Kashiwazaki, Taku Ogura, Kiyohiro Furutani
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Patent number: 7365578Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: July 3, 2007Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070285146Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: July 3, 2007Publication date: December 13, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi