Abstract: When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: A semiconductor memory device includes: a memory cell region constructed of blocks and a memory cell region constructed of blocks. The blocks and the blocks are continuously disposed. A block decoder outputs block select signals to the respective blocks. As a result, power consumption of the semiconductor memory device is reduced.

Abstract: Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Abstract: In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

Abstract: A semiconductor memory device includes: a memory cell region constructed of blocks and a memory cell region constructed of blocks. The blocks and the blocks are continuously disposed. A block decoder outputs block select signals to the respective blocks. As a result, power consumption of the semiconductor memory device is reduced.

Abstract: Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Abstract: A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.

Abstract: Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: An internal signal RAS generated in accordance with command input and indicating activation of a row is delayed in accordance with a dock signal int.CLKI, and thereby a sense amplifier activating signal is issued. A time from activation of a word line by a signal WLT to activation of a sense amplifier can be longer than that in a normal case so that a minute leak from a bit line can be detected.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: An internal signal RAS generated in accordance with command input and indicating activation of a row is delayed in accordance with a clock signal int.CLKI, and thereby a sense amplifier activating signal is issued. A time from activation of a word line by a signal WLT to activation of a sense amplifier can be longer than that in a normal case so that a minute leak from a bit line can be detected.

Abstract: Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Abstract: In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

Abstract: A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on.

Abstract: In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

Abstract: In an SDRAM chip, two signal generation circuits are provided corresponding to two test circuits arranged at either ends of a rectangular semiconductor substrate. Each signal generation circuit is provided in the proximity of corresponding test circuit. Hence, a signal line for test signal can be reduced and smaller chip area can be achieved compared with the conventional case where one signal generation circuit is provided at a center of the semiconductor substrate and a test signal is supplied to two test circuits from the signal generation circuit.