Abstract: A polysilicon film having a rough surface is formed by a reduced pressure CVD method at a temperature of 575.degree. C. and a deposition pressure of 0.2 Torr. Silicon ions are implanted into the polysilicon film having a rough surface. Thus, the tips of concaves and convexes at the rough surface of the polysilicon film are rounded. Then, this polysilicon film having a rough surface is patterned to form a storage node. A cell plate is formed to cover the storage node with a capacitor insulating layer therebetween. Consequently, a semiconductor device capable of suppressing leak current between capacitor electrodes can be manufactured.

Abstract: A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench that extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield.

Abstract: A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench hat extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain A region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield.

Abstract: A method of localized control of integrated circuit parameters according to the present invention is used to adjust a the threshold voltage of an integrated circuit by irradiating an inoperable area with a focused ion beam such that the determination of the correct threshold voltage is facilitated without having to refabricate the integrated circuit in its entirety.

Abstract: It is an object to obtain a semiconductor device free from a necessity of stacking a contact hole and a lower electrode, thus preventing occurrence of an error in stacking and enabling the capacitor to be formed precisely. Amorphous silicon 10b is deposited on a interlayer insulating film 9 including the inside portion of the contact hole 9a, and then a resist 14 is applied to the amorphous silicon 10b. Then, a mask for photolithography which has been used to form the contact hole 9a is used to perform a photolithography process to form the resist 14 to have a required shape. Then, implantation of phosphorus ions is performed such that the resist 14 is used as a mask 14a for preventing implantation of ions. Then, the amorphous silicon 10b is subjected to heat treatment to partially single crystallize the amorphous silicon 10b so that single crystal silicon 10c is grown.

Abstract: A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Abstract: In the semiconductor device according to the invention, a tubular storage node is formed, then slanting rotation implantation of impurity phosphorus ions is executed for changing the phosphorus concentration and the etching rate at the thermal phosphoric acid treatment time is changed for roughening the surface under good control. Since the surface roughening does not extend to the center of the film of the storage node, the strength of the storage node can be held sufficient. Therefore, the capacitance can be increased.

Abstract: A fuel tank device has a canister suitably mounted inside a fuel tank. The fuel tank device includes a tank body in which fuel is stored, a filler tube connected at one end to the tank body for supplying the fuel into the tank body, and a canister hung and supported by the edge of an opening formed through the tank body via a support member and a sealing member, for adsorbing and storing evaporative fuel generated in the tank body. The canister is mounted entirely within the tank body and located so as not to be directly exposed to the fuel when the fuel is being supplied from the filler tube.

Abstract: A storage node electrode formed of doped amorphous silicon is provided on a silicon substrate. Silicon crystal grains are formed on the surface of the storage node electrode by annealing it in the atmosphere including PH.sub.3. A capacitor insulating film and a cell plate electrode are formed to cover the surface of the storage node electrode including silicon crystal grains. Larger silicon crystal grains are accordingly provided on the surface of the storage node electrode, resulting in increased capacitance of the capacitor.

Abstract: A fuel evaporative emission treatment system includes a canister which has an evaporative fuel introduction part arranged for communication with a fuel tank, an evaporative fuel emission part arranged for communication with an intake system of an engine, and a vent part arranged for communication with the atmosphere, and which absorbs the evaporative fuel. The fuel evaporative emission treatment system includes a vent pipe having a first passage communicating to the vent part of the canister and to the atmosphere, a first solenoid valve for opening and closing the first passage, an air filter for cleaning atmospheric air flowing thereinto, the filter being provided on the first passage on the side remote from the canister with respect to the first solenoid valve, and a one-way valve or lead valve which defines a second passage communicating to the vent part of the canister. The valve is opened at fueling.

Abstract: The fuel storage system includes a control valve having a valve body which is movable along the inner circumferential wall surface of a filler pipe and which defines a passage isolated from the inner space of the filler pipe. A fuel tank and a canister communicate with each other via a main vapor line. When a fuel cap is attached to the filler port of the filler pipe, the valve body of the control valve is pushed by the fuel cap to be shifted away from the filler port, whereby a first sub-vapor line extending between the fuel tank and the control valve via the passage defined by the valve body is communicated to a second sub-vapor line extending between the control valve and the middle part of the main vapor line, permitting evaporative fuel gas to be introduced from the fuel tank into the canister.

Abstract: A polysilicon film having a rough surface is formed by a reduced pressure CVD method at a temperature of 575.degree. C. and a deposition pressure of 0.2 Torr. Silicon ions are implanted into the polysilicon film having a rough surface. Thus, the tips of concaves and convexes at the rough surface of the polysilicon film are rounded. Then, this polysilicon film having a rough surface is patterned to form a storage node. A cell plate is formed to cover the storage node with a capacitor insulating layer therebetween. Consequently, a semiconductor device capable of suppressing leak current between capacitor electrodes can be manufactured.

Abstract: A storage node electrode formed of doped amorphous silicon is provided on a silicon substrate. Silicon crystal grains are formed on the surface of the storage node electrode by annealing it in the atmosphere including PH.sub.3. A capacitor insulating film and a cell plate electrode are formed to cover the surface of the storage node electrode including silicon crystal grains. Larger silicon crystal grains are accordingly provided on the surface of the storage node electrode, resulting in increased capacitance of the capacitor.

Abstract: A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Abstract: A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked --a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

Abstract: A fuel evaporative emission treatment system installed in an engine fuel system has a canister for adsorbing evaporative fuel, a vent hose connecting a fuel tank and the canister, and a vent circulation hose connecting the vent hose and a filler neck of the fuel tank, and the sectional areas of the vent hose and vent circulation hose are set so that the ratio thereof may be a proper value. The negative pressure produced in the filler neck due to aspiration induced by refueling is canceled out by the pressure of fuel gas circulated to the filler neck through the vent circulation hose, whereby the internal pressure of the filler neck is controlled to a value appropriately smaller than the atmospheric pressure. Thus, inflow of the outside air into the filler neck, and thus generation of evaporative fuel gas, can be suppressed, and also the outflow of evaporative fuel gas from the filler neck is suppressed.

Abstract: A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode.

Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Abstract: A method for manufacturing expandable styrene type polymer particles is disclosed, which comprises the steps of adding a styrene type monomer to styrene type polymer seed particles suspended in an aqueous dispersing medium, continuously or intermittently to be polymerized while being absorbed thereby, and impregnating the resulting polymer particles with an easily volatile blowing agent to obtain expandable styrene type polymer particles, the improvement wherein styrene type polymer particles whose weight-average molecular weight (Mw.sub.1) is not more than 2/3 of the weight-average molecular weight (Mw.sub.2) of the resulting polymer particles are used as said styrene type polymer particles. The present invention provides expandable styrene type polymer particles excellent in moldability and foamed articles high in strength and fine in external appearance.

Abstract: The present invention provides a method for producing expandable thermoplastic polymer particles which comprises conducting polymerization by adding a polymerizable monomer either continuously or intermittently to thermoplastic polymer particles having a uniform particle size suspended in water, the improvement wherein an amide compound is added when the added amount of the polymerizable monomer is not more than one half of the total amount to be added in the course of polymerization and resulting polymer particles are impregnated with an easily volatile blowing agent after completion of addition of the amide compound and the polymerizable monomer. According to the present invention, expandable thermoplastic particles which are capable of giving cells, fine and uniform in size, are obtainable even by expanding immediately after production without any aging period.