Abstract: In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.

Abstract: Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silicon substrate 10. N-type impurities are injected into the NMOS regions (FIG. 1A). A WSi film 22 is formed on the amorphous silicon film 16, and N-type impurities are injected only into the PMOS regions of the film 16 (FIG. 1C). A silicon oxide film 28 and a silicon nitride film 30 are formed on the WSi film 22 and then etched into gate electrodes (FIG. 1E).

Abstract: In a fabrication method of semiconductor device, a storage node connected to one of source/drain regions of an MOS (Metal Oxide Semiconductor) transistor provided at a semiconductor substrate is formed along a trench provided through a silicon nitride film, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film and a silicon oxide film grown at low temperature. The silicon oxide film grown at low temperature is formed by either atmospheric pressure CVD (chemical vapor deposition) or plasma CVD. Also, a sidewall protection film is formed so as to prevent shorting between adjacent capacitors by growing a film at low temperature. Thus, a semiconductor device of high performance and high reliability can be provided even in a system LSI (Large Scale Integrated circuit) in which a memory circuit and logic circuit are embedded.

Abstract: Improvements are realized in the coverage characteristics of a cell plate electrode with respect to a cylindrical storage node electrode which has a high aspect ratio (height/diameter) and a surface having minute irregularities formed thereon, thereby improving the electrical characteristics and reliability of a semiconductor device. The semiconductor device is manufactured through a step of forming a first cell plate electrode film on a cylindrical storage node electrode, a process of implanting conductive impurities into the first cell plate electrode film, and a process of forming a second cell plate electrode film on the first cell plate electrode film.

Abstract: In a fabrication method of semiconductor device, a storage node connected to one of source/drain regions of an MOS (Metal Oxide Semiconductor) transistor provided at a semiconductor substrate is formed along a trench provided through a silicon nitride film, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film and a silicon oxide film grown at low temperature. The silicon oxide film grown at low temperature is formed by either atmospheric pressure CVD (chemical vapor deposition) or plasma CVD. Also, a sidewall protection film is formed so as to prevent shorting between adjacent capacitors by growing a film at low temperature. Thus, a semiconductor device of high performance and high reliability can be provided even in a system LSI (Large Scale Integrated circuit) in which a memory circuit and logic circuit are embedded.

Abstract: On the photo mask are drawn product patterns and mask dimension inspection marks to be arranged around the respective product patterns. Each of the mask dimension inspection marks includes a line pattern having a width equal to a line width of the product pattern. Further, each of the mask dimension inspection marks includes a reference pattern that is disposed adjacent to the line pattern. A width of the mask dimension inspection mark is wider than that of the line pattern.

Abstract: In a method of forming a minute pattern comprising a step of forming an interlayer insulating film on a substrate and a step of forming a plurality of holes in the interlayer dielectric film by means of etching, a proportion of total holes in the minute pattern is adjusted by forming dummy holes.

Abstract: A disk drive apparatus according to the present invention includes a horizontal guide mechanism and a vertical guide mechanism, which are disposed between a frame (10) and a slider (60) for slidably guiding the slider (60). The horizontal guide mechanism includes an engaging piece (69b) disposed in at least one of the frame (10) and the slider (60) and an engaging hole (24a), which is disposed in the other and is engaged with the engaging piece (69b). One of the frame (10) and the slider (60), in which the engaging piece (69b) is formed, is made of a metallic sheet material while the engaging piece (69b) is formed by bending part of the metallic sheet material.

Abstract: Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silicon substrate 10. N-type impurities are injected into the NMOS regions (FIG. 1A). A WSi film 22 is formed on the amorphous silicon film 16, and N-type impurities are injected only into the PMOS regions of the film 16 (FIG. 1C). A silicon oxide film 28 and a silicon nitride film 30 are formed on the WSi film 22 and then etched into gate electrodes (FIG. 1E).

Abstract: On the photo mask are drawn product patterns and mask dimension inspection marks to be arranged around the respective product patterns. Each of the mask dimension inspection marks includes a line pattern having a width equal to a line width of the product pattern. Further, each of the mask dimension inspection marks includes a reference pattern that is disposed adjacent to the line pattern. A width of the mask dimension inspection mark is wider than that of the line pattern.

Abstract: Tungsten wiring 12 is formed on top of a silicon substrate 1. Above the tungsten wiring 12 are formed silicon oxide films 13, 17 and 20; a silicon nitride film 16; or upper electrodes 20 made of a silicon film. Thicknesses of these films are measured on the tungsten wiring 12.

Abstract: A manufacturing method of a semiconductor device obtaining performances respectively required in a MOS transistor in semiconductor memories and a MOS transistor in logic devices even in case of manufacturing a system LSI combining the semiconductor memories with the logic devices. Forming silicide films 7 in a logic device region 11 makes it possible to reduce the resistivity of diffusion regions 9 and a conductive film 4 of polysilicon or the like that will serve as an electrode of a resulting MOS transistor. Therefore, the semiconductor devices can be manufactured in which such the MOS transistor can be used as the MOS transistor in the logic devices that is required to operate at high speed and the MOS transistor is also formed in a DRAM or the like where miniaturization is required. Since no alternation is made of the structures of the respective MOS transistors, a semiconductor device whose performance is equivalent to that of the conventional counterpart can be manufactured.

Abstract: After a bottom electrode 30 of a capacitor is formed, a nitride film as an insulating film 32 of the capacitor is formed on the bottom electrode 30 by CVD. Then, the insulating film 32 is wet-oxidized at a temperature in a range of 700° C. to 760° C. Finally, a top electrode 34 of the capacitor is formed on the insulating film 32. The insulating film 32 forming step includes a substep of increasing the temperature of a silicon wafer to a CVD reaction temperature in an ammonia atmosphere.

Abstract: In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.

Abstract: In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.

Abstract: A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry.

Abstract: A method of manufacturing a semiconductor device including a capacitor having an increased capacity with improved yield is provided. Ions are implanted at an incidence angle of 0° in a dose of 8×1015atom/cm2, at an energy of 20 keV, using a heavy current device and an amorphous silicon film having an upper surface flattened is formed. Only the flattened amorphous silicon film formed on the upper surface of an interlayer oxide film is etched back to form a storage electrode.

Abstract: A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry.

Abstract: An amorphous silicon film is formed on an interlayer insulating film to cover an upper surface of the interlayer insulating film, and a side surface and a bottom surface of an opening formed at the interlayer insulating film. Phosphorus ions are implanted into the amorphous silicon film. The phosphorous ions are implanted into the amorphous silicon film located on the upper surface of the interlayer insulating film to prevent crystal grains from growing, and thus a polysilicon film having no hemispherical grains is formed. Accordingly, a semiconductor device having capacitors with respective storage nodes adjacent to each other that are electrically isolated properly is obtained.

Abstract: A polysilicon film having a rough surface is formed by a reduced pressure CVD method at a temperature of 575.degree. C. and a deposition pressure of 0.2 Torr. Silicon ions are implanted into the polysilicon film having a rough surface. Thus, the tips of concaves and convexes at the rough surface of the polysilicon film are rounded. Then, this polysilicon film having a rough surface is patterned to form a storage node. A cell plate is formed to cover the storage node with a capacitor insulating layer therebetween. Consequently, a semiconductor device capable of suppressing leak current between capacitor electrodes can be manufactured.