Patents by Inventor Kiyoshi Nakai
Kiyoshi Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869580Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.Type: GrantFiled: December 30, 2021Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Tomohiko Yamagishi, Seiji Narui, Kiyoshi Nakai, Takamasa Suzuki
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Patent number: 11854601Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.Type: GrantFiled: December 28, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Kiyoshi Nakai, Seiji Narui
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Patent number: 11740964Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.Type: GrantFiled: September 21, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventor: Kiyoshi Nakai
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Patent number: 11709731Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.Type: GrantFiled: May 12, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventor: Kiyoshi Nakai
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Publication number: 20230215494Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Tomohiko Yamagishi, Seiji Narui, Kiyoshi Nakai, Takamasa Suzuki
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Publication number: 20230206985Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Kiyoshi Nakai, Seiji Narui
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Publication number: 20220199137Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: ApplicationFiled: December 28, 2021Publication date: June 23, 2022Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Publication number: 20220114049Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.Type: ApplicationFiled: September 21, 2021Publication date: April 14, 2022Inventor: Kiyoshi Nakai
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Patent number: 11217291Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: GrantFiled: July 11, 2019Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Publication number: 20210342222Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.Type: ApplicationFiled: May 12, 2021Publication date: November 4, 2021Inventor: Kiyoshi Nakai
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Patent number: 11132253Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.Type: GrantFiled: December 6, 2018Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventor: Kiyoshi Nakai
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Patent number: 11016843Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.Type: GrantFiled: December 6, 2018Date of Patent: May 25, 2021Assignee: Micron Technology, Inc.Inventor: Kiyoshi Nakai
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Publication number: 20210012825Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Publication number: 20200183782Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Inventor: Kiyoshi Nakai
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Publication number: 20200183781Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Inventor: Kiyoshi Nakai
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Publication number: 20140092679Abstract: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.Type: ApplicationFiled: December 4, 2013Publication date: April 3, 2014Applicant: Elpida Memory, Inc.Inventors: Koji Sato, Kiyoshi Nakai, Kenji Mae
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Patent number: 8605494Abstract: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.Type: GrantFiled: November 16, 2009Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventors: Koji Sato, Kiyoshi Nakai, Kenji Mae
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Publication number: 20130242641Abstract: A semiconductor device includes: a plurality of variable resistance memory cells; a plurality of bit lines each of which is connected to one end of each of the plurality of variable resistance memory cells; a common source line that is connected to the other ends of the plurality of variable resistance memory cells in common; a source line driver that supplies a potential to the common source line; and a controller that variably controls a current supplied to the common source line by the source line driver.Type: ApplicationFiled: March 12, 2013Publication date: September 19, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Kiyoshi NAKAI
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Patent number: 8116154Abstract: To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier is requested while a data write operation using a predetermined write amplifier is performed, the write control circuit suspends the data write operation using the predetermined write amplifier. The suspended data write operation is performed again simultaneously with the data write operation using the other write amplifier. Accordingly, random column access like that of a DRAM can be realized by simple control.Type: GrantFiled: January 21, 2010Date of Patent: February 14, 2012Assignee: Elpida Memory, Inc.Inventor: Kiyoshi Nakai
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Patent number: RE45753Abstract: A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.Type: GrantFiled: January 10, 2014Date of Patent: October 13, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Kiyoshi Nakai, Shuichi Tsukada