Abstract: A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

Abstract: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

Abstract: A phase change memory device has a memory cell that uses a phase change film as a storage element, and includes: a first phase change region formed on a side of one face of the phase change film; and a second phase change region formed on a side of another face of the phase change film in a position that corresponds to the first phase change region, wherein the phase change memory stores two-bit data using combinations of a high resistance state due to amorphization and a low resistance state due to crystallization in the first phase change region with the high resistance state and the low resistance state in the second phase change region, the resistance value of the low resistance state being lower than that of the high resistance state.

Abstract: A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.

Abstract: Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell for the time duration of a preset number of cycles until start of data write, a transfer switch that controls whether or not an output of the read data latch is to be transferred to the write data latch, a comparator circuit that decides whether or not data transferred to the write data latch via the transfer switch and held in the write data latch and data in the read data latch are coincident with each other, and a write flag latch that latches an output of the comparator circuit. Data is written only in case there is a write request and the result of comparison of the comparator circuit indicates non-coincidence, that is, only in bits in need of data writing.

Abstract: A semiconductor memory device according to the present invention has a storage unit that includes an interlayer insulation film, a lower electrode layer embedded in the interlayer insulation film, and a recording layer and an upper electrode layer provided on the interlayer insulation film. When a predetermined current is passed to the storage unit, the recording layer is heated by substantially exceeding a melting point, and a cavity is formed near the interface between the recording layer and the lower electrode layer. As a result, the recording layer is physically separated from the lower electrode layer, and no current flows through the storage unit. When the recording layer is physically separated from the lower electrode layer, these layers cannot be returned to the contact state again. Therefore, information can be stored irreversibly.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: To provide a nonvolatile memory including a word-line drive circuit that supplies a selective voltage to a selective transistor connected in series to a nonvolatile memory device. The word-line drive circuit applies a first selective voltage VDD to a control electrode of the selective transistor in a first period, and applies a second selective voltage VPP higher than the first selective voltage VDD to the control electrode of the selective transistor in a second period that follows the first period. Thereby, a current drive capability of the selective transistor is gradually changed. Thus, it becomes possible to limit the current drive capability of the selective transistor at timing at which snap-back is caused. As a result, an excessive current caused by the snap-back is suppressed, thereby reducing damage inflicted on the nonvolatile memory device.

Abstract: Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected to write amplifier, second end connected to the bit line, and a gate, and controlled such that, if the write amplifier outputs a voltage level on power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the power-supply voltage and exceeding the voltage level of the power supply is applied to the gate. A second NMOS transistor has first end to which the block-select activating signal is applied, a gate connected to the power supply, and second end connected to the gate of the first NMOS transistor.

Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly connected to a source line, and the drain regions are each connected to a lower electrode of a different memory element. According to the present invention, it is possible to assign three cell transistors connected in parallel to one memory element, so that an effective gate width is further increased.

Abstract: A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.

Abstract: A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.

Abstract: A non-volatile memory element includes a recording layer that includes a phase change material, a lower electrode provided in contact with the recording layer, an upper electrode provided in contact with a portion of the upper surface of the recording layer, a protective insulation film provided in contact with the other portion of the upper surface of the recording layer, and an interlayer insulation film provided on the protective insulation film. High thermal efficiency can thereby be obtained because the size of the area of contact between the recording layer and the upper electrode is reduced. Providing the protective insulation film between the interlayer insulation film and the upper surface of the recording layer makes it possible to reduce damage sustained by the recording layer during patterning of the recording layer or during formation of the through-hole for exposing a portion of the recording layer.

Abstract: An apparatus has a one-dimensional analysis column for separating a sample into a plurality of components, a preparative portion for fractionating the separated components, component by component and for keeping a fractionated component, a plurality of trap columns for trapping a component supplied from the preparative portion, a two-dimensional analysis column for further separating a component trapped in the trap columns, into a plurality of components, and a path switching mechanism for effecting switching between a state in which the preparative portion is connected to a first trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to a second trap column out of the plurality of trap columns, and a state in which the preparative portion is connected to the second trap column out of the plurality of trap columns and in which the two-dimensional analysis column is connected to the first trap column out of the plurality of trap columns.

Abstract: A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

Abstract: A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.