Abstract: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

Abstract: A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A semiconductor memory device is provided which is capable of correcting efficiently bits having a low error rate in a Pause Refresh Tail distribution and of greatly reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM (Synchronous Dynamic Random Access Memory) having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of a encoding circuit being controlled by a first test signal to output by arithmetic operations a parity bit corresponding to an information bit, a decoding circuit being controlled by a second test signal to output an error location detecting signal indicating an error bit in bits of a codeword, and an error correcting circuit being controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.

Abstract: A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL2a) are formed on a first layer, and lines M2 (e.g., M2a) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL1c) are formed on the first layer, and lines M2 (e.g., M2c) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M2 on the second layer can have a smaller line interval.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

Abstract: A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

Abstract: A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

Abstract: A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group.

Abstract: A method of producing a porous metal, which comprises forming a mixture of a metal powder and a fibrous substance and subjecting the mixture to sintering treatment to obtain a porous metal; a catalyst carrier obtained by laminating a dried sheet wherein a metal powder is supported in a fibrous substance with a dried sheet obtained by corrugating a dried sheet similar to the first-mentioned sheet to form an assembly of a number of cells having both ends opened and subjecting the assembly to sintering treatment; and a filter element obtained by laminating a dried sheet wherein a metal powder is supported in a fibrous substance with a dried sheet obtained by corrugating a dried sheet similar to the first-mentioned sheet to form an assembly of a number of cells whose one end is opened and whose other end is closed and subjecting the assembly to sintering treatment.

Abstract: m-Isopropenylphenol oligomer which is useful for the production of synthetic resins such as epoxy resins is produced by polyermizing m-isopropenylphenol at a temperature of 135.degree. to 230.degree. C. using a catalytic amount of an acid catalyst in the presence or absence of a solvent, or freezing m-isopropenylphenol in the presence or absence of an acid catalyst.