Abstract: A semiconductor memory device has a plurality of memory cells, each having a ferroelectric memory capacitor, arranged in a matrix formation in rows and columns. A read-out device is associated with each row for reading out data stored in a selected one of the memory cells in the row based on voltages generated by the ferroelectric capacitor belonging to that selected memory cell and a plurality of divided ferroelectric capacitors which are distributed in the direction of the rows such that piezoelectric effects on the ferroelectric capacitors will be diminished.

Abstract: A switch SW 11 comprises a ferroelectric memory 26 and an AND gate 28. A data input line L11 and an output terminal of the ferroelectric memory 26 are connected to an input terminal of the AND gate 28. Also, the output terminal of the AND gate 28 is connected to an AND input line L21. In order to write the switching data which switches the state of the switch SW11 either to an open state or a closed state into the ferroelectric capacitor 26, ferroelectric capacitors C11 and C12 are polarized in opposite directions with each other. The polarization is carried out in a short period, and the polarization state can be maintained even when the power is turned off. So that, the switching data can be written repeatedly by changing direction of the voltage applied to the ferroelectric capacitors C11 and C12.

Abstract: A ferroelectric memory device has a ferroelectric memory capacitor with a hysteresis characteristic adapted to store either a first memory content corresponding to a first polarization condition or a second memory content corresponding to a second polarization condition when there is no applied voltage. A first load capacitor is connected in series with the memory capacitor, and a second load capacitor is connected in series with a reference capacitor. The first and second capacitors are both ferroelectric capacitors and have substantially the same characteristics as the memory capacitor.

Abstract: A ferroelectric memory device has a ferroelectric memory capacitor with a hysteresis characteristic adapted to store either a first memory content corresponding to a first polarization condition or a second memory content corresponding to a second polarization condition when there is no applied voltage. A load capacitor is connected in series with the memory capacitor at least at a readout time when the content of the memory capacitor is read out with a readout voltage applied to this series connection. The readout voltage has a polarity different from that of the voltage which will result in the first polarization condition. The memory content of the memory capacitor is determined from the partial voltage generated across the memory capacitor when the readout voltage is applied. A rewrite voltage is applied to the memory capacitor for recovering the polarization condition corresponding to the memory content.

Abstract: On completion of a test for data storing characteristics under a condition of the wafer (step S4), the test data are rewritten to the data having inverted data pattern (step S6). Thereafter, package-sealing process is carried out (step S8). Then, the conditions of the test for data storing characteristics after packaging the memory are set (step S10). Set of the conditions is carried out by calculating the data pattern of a step for heating under data storing condition, heating duration and heating temperature, all of which will be carried out in the next process in accordance with the stress calculated in every data pattern as to the step S4 and the step S8 which have been completed.

Abstract: A nonvolatile memory with a simple structure where recorded information can be read without destruction. A voltage is impressed between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the direction of the impressed voltage. A control gate voltage to make channel is small when the ferroelectric layer is polarized with the control gate side being positive. Control gate voltage to make channel is large when the ferroelectric layer is polarized with the control gate side being negative. The reference voltage is impressed on the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with a second polarization and a small drain current flows when the ferroelectric layer is polarized with a first polarization. Record information can be read by detecting the drain current. Polarization status of the ferroelectric is not destroyed in the reading operation.

Abstract: When a rewriting instruction data is provided to an instruction decoder from a read only memory for a program, the instruction decoder decodes the data and provides an instruction rewriting control signal to a writing block. Thereby, the writing block receives a data following the writing instruction data from the ROM and writes the received data in the rewritable area of the instruction decoder. When an instruction data is provided to the instruction decoder from the read only memory under this condition, an instruction which is different from the instruction therefor output when there is no rewriting instruction is therefor output based on the same instruction.

Abstract: Nonvolatile memory with a simple structure where recorded information can be read without destruction: Voltage is impressed between control gate CG and memory gate MG at a writing operation. A ferroelectric layer 32 is polarized in accordance with the direction of the impressed voltage. The control gate voltage V.sub.CG to make a channel is low when the ferroelectric layer 32 is polarized with the control gate side being positive (polarized with second status). The control gate voltage V.sub.CG to make a channel is high when the ferroelectric layer 32 is polarized with the control gate side being negative (polarized with the first status). The reference voltage V.sub.ref is impressed to the control gate CG at the reading operation. A high drain current flows when the ferroelectric layer is polarized with the second status and low drain current flows when the ferroelectric layer is polarized with the first status. Recorded information can be read by detecting the drain current.

Abstract: A nonvolatile memory having a simple structure where recorded information can be read nondestructively. A voltage is applied between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the polarization of the applied voltage. A control gate voltage, necessary to form a channel, is small when the ferroelectric layer is polarized with the control gate side negative (polarized with second polarization). The control gate voltage V.sub.cg necessary to form a channel is large when the ferroelectric layer is polarized with the control gate side positive (polarized with first polarization). The reference voltage is applied to the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with the second polarization and a small drain current flows when the ferroelectric layer is polarized with the first polarization. Recorded information can be read by detecting the drain current.

Abstract: Nonvolatile memory with simple structure where recorded information can be read without destroy: Voltage is impressed to control gate CG and channel is grounded at writing operation. Ferroelectric layer 32 is polarized in accordance with whether the applied voltage is larger than threshold voltage of the memory device. Control gate voltage V.sub.CC to make channel is little when the ferro-electric layer 32 is polarized with control gate side being positive (polarized with second status). Control gate voltage V.sub.CG to make channel is large when the ferroelectric layer 32 is polarized with control gate side being negative (polarized with first status). The reference voltage V.sub.ref is impressed to the control gate CG at reading operation. Large drain current flows when the ferroelectric layer is polarized with second status and little drain current flows when the ferroelectric layer is polarized with first status. Recorded information can be read by detecting the drain current.

Abstract: A fuzzy controller includes a fuzzy reasoner, a rule storage, a membership function storage and an extractor. The rule and the membership function storages are constituted by rewritable memories such as an EEPROM, and provide to the fuzzy reasoner a reasoning rule and a membership function, respectively. The extractor provides, in accordance with an input and an output signals of the fuzzy reasoner, a reasoning rule and a membership function stored therein in advance to the rule and membership function storages. The data previously stored in the rule and membership function storages are replaced by the data transmitted from the extractor.