Abstract: A measurement apparatus comprising: a clock generator configured to generate a sampling clock having a longer sampling cycle than a symbol cycle in a pattern under test including a symbol with a predefined number of symbols; a sampler configured to sample, according to the sampling clock, the pattern under test that is repeatedly inputted; and a measuring section configured to measure a sampling result of the sampler according to the sampling clock of a time point corresponding to a symbol transition that becomes subject to jitter measurements in the pattern under test that is repeatedly inputted.

Abstract: A signal processor is provided, comprising a data variable delay circuit that delays data signals, a clock variable delay circuit that delays a clock signal indicating timing to acquire the data signals, a jitter signal supplying unit that supplies, to the data variable delay circuit and the clock variable delay circuit, a jitter signal to change an amount of delay in a same direction, and a re-timing circuit that outputs a jitter-applied data signal obtained by re-timing the data signals delayed by the data variable delay circuit with the clock signal delayed by the clock variable delay circuit.

Abstract: A signal processor is provided, comprising a data variable delay circuit that delays data signals, a clock variable delay circuit that delays a clock signal indicating timing to acquire the data signals, a jitter signal supplying unit that supplies, to the data variable delay circuit and the clock variable delay circuit, a jitter signal to change an amount of delay in a same direction, and a re-timing circuit that outputs a jitter-applied data signal obtained by re-timing the data signals delayed by the data variable delay circuit with the clock signal delayed by the clock variable delay circuit.

Abstract: Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level.

Abstract: A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.

Abstract: Provided are a transmitting system including a pulse amplitude modulator section that pulse amplitude modulates an input signal into a set of first and second pulse amplitude modulated signals, a first frequency signal output section that outputs a first frequency signal, a first amplitude shift keying modulator section that amplitude shift keying modulates, using the first frequency signal, the first pulse amplitude modulated signal into an amplitude shift keying modulated signal, an adder section that adds together the amplitude shift keying modulated signal and the second pulse amplitude modulated signal to generate a transmission signal, and a transmitter section that transmits the transmission signal, a transmitting method, a receiving system for receiving the signal transmitted from the transmitting system and a receiving method.

Abstract: A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

Abstract: A pattern generator PG generates control data which specifies a threshold voltage to be compared with a signal under test input to an I/O terminal, and generates expected value data which represents an expected value for the comparison result between the signal under test and the threshold voltage. A threshold voltage generator generates the threshold voltage having a voltage level that corresponds to the control data at every setting timing indicated by a first timing signal. A level comparator compares the voltage level of the signal under test with its corresponding threshold voltage. A timing comparator latches the output of the level comparator at a strobe timing indicated by a second timing signal so as to generate a comparison signal. A timing adjustment unit adjusts the phase of the first timing signal.

Abstract: There is provided a deterministic component model identifying apparatus for determining a type of a deterministic component contained in a probability density function supplied thereto.

Abstract: Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level.

Abstract: There is provided a jitter measurement apparatus to measure jitter of a signal under measurement. The jitter measurement apparatus includes a pulse generator that outputs a demodulated signal indicating the jitter of the signal under measurement, by outputting a pulse having a substantially constant pulse width in synchronization with each predetermined edge of the signal under measurement, a DC component detecting section that detects a DC component of the demodulated signal output from the pulse generator, and an adjusting section that adjusts the pulse width of the pulse output from the pulse generator, based on the DC component of the demodulated signal which is detected by the DC component detecting section.

Abstract: Provided is an evaluation apparatus that evaluates a characteristic of a propagation apparatus propagating a signal, comprising an output signal measuring section that measures a probability density function expressing a probability density distribution of jitter of an output signal passed by the propagation apparatus; an isolating section that isolates at least one of a random component of a jitter component and a deterministic component of the jitter component in the jitter of the output signal, from the probability density function of the jitter of the output signal; and an evaluating section that evaluates the characteristic of the propagation apparatus based on the jitter component isolated by the isolating section.

Abstract: There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform.

Abstract: There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, having a pulse generator for outputting a pulse signal having a pulse width set in advance corresponding to edges-under-measurement from which the timing jitter is to be measured in the signal-under-measurement, a filter for removing carrier frequency components of the signal-under-measurement from the pulse signal and a jitter calculator for calculating the jitter in the signal-under-measurement based on the signal outputted out of the filter.

Abstract: There is provided a jitter amplifier circuit for amplifying jitter included in an input signal. The jitter amplifier circuit includes a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate a harmonic component of the input signal, and a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.

Abstract: Provided is a digital modulator, including a carrier wave output section that outputs a carrier wave, a variable delay section that delays the carrier wave, and a delay amount setting section that sets a delay amount by which the variable delay section delays the carrier wave based on transmission data being transmitted by the carrier wave. The variable delay section may include a multi-stage delay buffer circuit in which delay buffers that delay an input signal by a unit shift amount are connected in a cascade connection, the multi-stage delay buffer circuit may receive the carrier wave at a first-stage delay buffer as input, and the delay amount setting section may include a multiplexer that selects either an output from the carrier wave output section or an output from each stage of the multi-stage delay buffer circuit.

Abstract: Provided is a deterministic component model determining apparatus that determines a type of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; a theoretical value calculating section that calculates a theoretical value of a spectrum for each of a plurality of predetermined types of deterministic components, based on the null frequency; a measured value calculating section that calculates a measured value of the spectrum for the deterministic component included in the probability density function, based on the standard deviation and the spectrum; and a model determining section that determines the type of the deterministic component included in the probability density function

Abstract: Provided is a phase detecting apparatus that detects a phase difference between signals, comprising a phase comparing section that sequentially delays a second input signal relative to a first input signal, according to a set value, and that compares a phase of the second input signal to a phase of the first input signal each time a relative phase between the input signals changes; and a delay adjusting section that adjusts in advance a delay amount of a signal in the phase comparing section.