Patents by Inventor Kiyotaka Ichiyama

Kiyotaka Ichiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090189666
    Abstract: Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: ADVANTEST CORPORATION
    Inventors: KIYOTAKA ICHIYAMA, MASAHIRO ISHIDA
  • Publication number: 20090189667
    Abstract: Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Applicant: ADVANTEST CORPORATION
    Inventors: KIYOTAKA ICHIYAMA, MASAHIRO ISHIDA
  • Patent number: 7564897
    Abstract: A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: July 21, 2009
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi, Mani Soma
  • Patent number: 7554332
    Abstract: There is provided a calibration apparatus for calibrating an electronic device that outputs a demodulation signal in which a modulated component of a signal to be tested or evaluated is demodulated, having a DC component detecting section for detecting a DC component of the demodulation signal, a gain calculating section for calculating a gain in the electronic device based on the DC component of the demodulation signal and a calibrating section for calibrating the electronic device based on the gain in the electronic device.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: June 30, 2009
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi
  • Patent number: 7541815
    Abstract: A testing apparatus tests the performance of an electronic device having an operation circuit for providing a useful output signal. A demodulator configured to provide a phase or frequency demodulated signal related to the output of the operation circuit is packaged with the operation circuit. The gain of the demodulator is controllable from outside the package. The testing apparatus analyses the demodulated signal and controls the gain of the demodulator.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: June 2, 2009
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi
  • Publication number: 20090103672
    Abstract: There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 23, 2009
    Applicant: ADVANTEST CORPORATION
    Inventors: KIYOTAKA ICHIYAMA, MASAHIRO ISHIDA
  • Patent number: 7501905
    Abstract: An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes: a voltage controlled oscillator that outputs the oscillation signal with a frequency corresponding to a provided control voltage; and a jitter demodulator that extracts a phase fluctuation component of the oscillation signal outputted by the voltage controlled oscillator and modulates the control voltage according to the phase fluctuation component. The oscillator circuit may further include a low pass filter that removes a frequency component larger than a predetermined cutoff frequency of the control frequency inputted to the voltage controlled oscillator and provides the same to the voltage controlled oscillator.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: March 10, 2009
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Patent number: 7496137
    Abstract: There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, including a pulse generating section having first pulse generating means for detecting edges of the data-signal-under-measurement to output a first pulse signal having a pulse width set in advance corresponding to the edge and second pulse generating means for detecting boundaries of data sections where data values do not change in the data-signal-under-measurement to output a second pulse signal having a pulse width set in advance over the edge timings of the boundaries of the detected data sections and a jitter calculating section for calculating timing jitter in the data-signal-under-measurement based on the first and second pulse signals.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: February 24, 2009
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi, Mani Soma
  • Publication number: 20080310489
    Abstract: A communication system in which a signal is transferred includes a transmitter that transmits a signal, a receiver that receives a signal transmitted thereto, and an adaptive equalizer that generates a compensated signal by compensating degradation of the signal to be received by the receiver. The adaptive equalizer includes a signal compensating section that generates the compensated signal by passing therethrough the signal to be received by the receiver, a jitter measuring section that measures jitter of the compensated signal output from the signal compensating section, and an adjusting section that adjusts a characteristic of the signal compensating section so as to reduce the jitter of the compensated signal which is measured by the jitter measuring section.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: KIYOTAKA ICHIYAMA, MASAHIRO ISHIDA
  • Patent number: 7466140
    Abstract: There is provided a signal generation circuit for generating an output signal including jitter injected thereto. The signal generation circuit includes a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from each other, a carrier output section that outputs a carrier signal having a frequency positioned in substantially the middle between the frequencies of the first and second jitter signals, and an adding section that adds together the first jitter signal, second jitter signal and carrier signal so as to generate the output signal.
    Type: Grant
    Filed: December 25, 2006
    Date of Patent: December 16, 2008
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Publication number: 20080304580
    Abstract: There is provided a transmission system in which a data sequence is transmitted. The transmission system includes a transmitter that generates a transmission signal by converting pieces of data included in the data sequence into data waveforms each of which has (i) a level signal whose signal level is determined by a value of a corresponding one of the pieces of data and (ii) a timing edge indicating a timing to obtain the level signal, and transmits the generated transmission signal, and a receiver that detects the signal level of each of the data waveforms of the received transmission signal at the timing designated by the timing edge of the each data waveform, and outputs a data value corresponding to the detected signal level.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Applicant: ADVANTEST CORPORATION
    Inventor: KIYOTAKA ICHIYAMA
  • Patent number: 7412341
    Abstract: There is provided a jitter amplifier for amplifying or attenuating a jitter component contained in an input signal, having a jitter demodulating section for demodulating the jitter component from the input signal and an amplifying circuit for amplifying or attenuating the jitter component by controlling phase of the input signal based on the jitter component.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: August 12, 2008
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi
  • Patent number: 7394277
    Abstract: There is provided a testing apparatus for evaluating a device-under-test, having an extracting section for extracting jitter components out of an output signal outputted out of the device-under-test, a filter for passing predetermined frequency components in the jitter components, a phase control section for controlling phase of the output signal based on the jitter components outputted out of the filter and an evaluating section for evaluating the device-under-test based on a signal outputted out of the phase control section.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: July 1, 2008
    Assignee: Advantest Corporation
    Inventors: Masahiro Ishida, Kiyotaka Ichiyama, Takahiro Yamaguchi
  • Publication number: 20080150603
    Abstract: There is provided a signal generation circuit for generating an output signal including jitter injected thereto. The signal generation circuit includes a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from each other, a carrier output section that outputs a carrier signal having a frequency positioned in substantially the middle between the frequencies of the first and second jitter signals, and an adding section that adds together the first jitter signal, second jitter signal and carrier signal so as to generate the output signal.
    Type: Application
    Filed: December 25, 2006
    Publication date: June 26, 2008
    Applicant: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Publication number: 20080151981
    Abstract: There is provided a jitter amplifier circuit for amplifying jitter included in an input signal. The jitter amplifier circuit includes a distorting circuit that receives the input signal, and distorts a waveform of the input signal so as to generate a harmonic component of the input signal, and a filter that passes, out of the distorted signal output from the distorting circuit, a harmonic component of a certain order which is determined in accordance with an amplification ratio of amplifying the jitter.
    Type: Application
    Filed: December 25, 2006
    Publication date: June 26, 2008
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Publication number: 20080143453
    Abstract: An oscillator circuit that generates an oscillation signal is provided. The oscillator circuit includes: a voltage controlled oscillator that outputs the oscillation signal with a frequency corresponding to a provided control voltage; and a jitter demodulator that extracts a phase fluctuation component of the oscillation signal outputted by the voltage controlled oscillator and modulates the control voltage according to the phase fluctuation component. The oscillator circuit may further include a low pass filter that removes a frequency component larger than a predetermined cutoff frequency of the control frequency inputted to the voltage controlled oscillator and provides the same to the voltage controlled oscillator.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Publication number: 20080092000
    Abstract: There is provided a delay circuit that delays and outputs a given input signal. The delay circuit includes a first delaying section that delays the input signal, a second delaying section that further delays the input signal delayed by the first delaying section, and a delay setting section that sets a time delay in the second delaying section at a timing delayed by a predetermined time to a timing setting a time delay in the first delaying section.
    Type: Application
    Filed: September 26, 2006
    Publication date: April 17, 2008
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamagochi
  • Publication number: 20080077342
    Abstract: There is provided a jitter measurement apparatus for measuring a jitter of a data signal having a substantially constant data rate. The jitter measurement apparatus includes therein a signal converting section that converts the data signal into a clock signal, where the clock signal retains timings of data transition edges of the data signal at which a data value of the data signal transits and has edges whose cycle is substantially equal to the data rate, an analytic signal generating section that converts the clock signal into an analytic signal of a complex number, and a jitter measuring section that measures the jitter of the data signal based on the analytic signal.
    Type: Application
    Filed: September 26, 2006
    Publication date: March 27, 2008
    Inventors: Kiyotaka ICHIYAMA, Masahiro Ishida, Takahiro Yamaguchi
  • Publication number: 20070247181
    Abstract: There is provided a testing apparatus for evaluating a device-under-test, having an extracting section for extracting jitter components out of an output signal outputted out of the device-under-test, a filter for passing predetermined frequency components in the jitter components, a phase control section for controlling phase of the output signal based on the jitter components outputted out of the filter and an evaluating section for evaluating the device-under-test based on a signal outputted out of the phase control section.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 25, 2007
    Applicant: ADVANTEST CORPORATION
    Inventors: Masahiro Ishida, Kiyotaka Ichiyama, Takahiro Yamaguchi
  • Publication number: 20070239388
    Abstract: There is provided a jitter amplifier for amplifying or attenuating a jitter component contained in an input signal, having a jitter demodulating section for demodulating the jitter component from the input signal and an amplifying circuit for amplifying or attenuating the jitter component by controlling phase of the input signal based on the jitter component.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida, Takahiro Yamaguchi