Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: The present invention suppresses the strength reduction or degeneration of a tissue after the tissue is dried and/or sterilized, for the tissue comprising biological components and the like. Specifically, biological tissue is immersed in a trehalose solution and shaken, thereby impregnating the biological tissue with the trehalose solution. The trehalose solution used here is one obtained by dissolving trehalose in a phosphate buffered saline, the concentration of trehalose being preferably in the range of 20 wt % to 35 wt %. Thereafter, the biological tissue is dried to remove moisture in the biological tissue, and sterilized with ethylene oxide gas.

Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a memory system is configured to include a nonvolatile memory and a controller circuit. The controller circuit is electrically connected to the nonvolatile memory. The controller circuit executes a first process and a second process. The first process manages a history of accesses to first storage areas of the nonvolatile memory. The second process manages a progress of accesses to all storage areas of the first storage areas within a first time limit, based on the history of the accesses.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

Abstract: According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a first controller. The first controller is configured to instruct to the storage medium to, after instructing the storage medium to write data into the first cell transistor and before completion of the writing of the data into the first cell transistor, suspend a process being performed to the first cell transistor, read data from the first data latch, read data from the second data latch, and read data from the first cell transistor.

Abstract: When receiving a write command from a host, a memory system according to one embodiment updates first correspondence information indicating the correspondence relationship between a logical address corresponding to user data and a position in a first memory and transmits the user data which has been stored in a second memory to the first memory. When the transmission is completed, the memory system writes the user data to the first memory. When the update and the transmission are completed, the memory system releases a memory area which stores the user data such that the memory area can be used as a memory area for other data.

Abstract: According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a first controller. The first controller is configured to instruct to the storage medium to, after instructing the storage medium to write data into the first cell transistor and before completion of the writing of the data into the first cell transistor, suspend a process being performed to the first cell transistor, read data from the first data latch, read data from the second data latch, and read data from the first cell transistor.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: A tensile testing machine exerts tensile force to biological, tissue attached to a bone. A fixture 10 according to the present invention includes a holder 11, which holds a bone B, and a support 12, which supports the holder 11. The holder 11 is provided with around-bone-axis angle adjusting mechanisms 14, 15, which adjust the angle of rotation of the bone B around the bone axis of the hone B held by the holder 11. The holder 11 and the support 12 are provided with bone inclination angle adjusting mechanisms 15, 34, which adjust the inclination angle of the bone B held by the holder 11. The support 12 is provided with lateral position adjusting mechanisms 34, 35, which adjust the lateral position of the holder 11 and longitudinal position adjusting mechanisms 35, 36, which adjust the longitudinal position of the holder 11.

Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.

Abstract: According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.

Abstract: According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.

Abstract: A memory device includes a nonvolatile memory unit including a plurality of banks, and a memory controller. The memory controller is configured to divide write data received from a host into a plurality of data portions, and with respect to each of the data portions, determine a bank in which said data portion is to be written and generate a write command to write said data portion to the determined bank. The memory controller determines the bank in which each of the data portions is to be written, based on the number of write commands queued for each of the banks.

Abstract: When receiving a write command from a host, a memory system according to one embodiment updates first correspondence information indicating the correspondence relationship between a logical address corresponding to user data and a position in a first memory and transmits the user data which has been stored in a second memory to the first memory. When the transmission is completed, the memory system writes the user data to the first memory. When the update and the transmission are completed, the memory system releases a memory area which stores the user data such that the memory area can be used as a memory area for other data.