Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.

Abstract: According to one embodiment, a controller includes a first command queuing part corresponding to a first bank, the first command queuing part queuing commands, a second command queuing part corresponding to a second bank, the second command queuing part queuing commands, and a bank control part which is configured to generate a first bound command by binding at least two commands in the first command queuing part, generate a second bound command by binding at least two commands in the second command queuing part, transfer the first bound command as an unit of an interleave operation between the first and second banks to the first bank, and transfer the second bound command as an unit of the interleave operation to the second bank.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: The present invention suppresses the strength reduction or degeneration of a tissue after the tissue is dried and/or sterilized, for the tissue comprising biological components and the like. Specifically, biological tissue is immersed in a trehalose solution and shaken, thereby impregnating the biological tissue with the trehalose solution. The trehalose solution used here is one obtained by dissolving trehalose in a phosphate buffered saline, the concentration of trehalose being preferably in the range of 20 wt % to 35 wt %. Thereafter, the biological tissue is dried to remove moisture in the biological tissue, and sterilized with ethylene oxide gas.

Abstract: A nonvolatile memory device includes a plurality of memory regions, and a memory controller that controls data transfer operations to and from the memory regions. When generating an error checking and correcting code (ECC) for data including a plurality of data units and writing the data and the ECC in at least one of a plurality of memory regions, the memory controller acquires ECC information and adjusts a size of the data units and a size of the ECC on the basis of the acquired ECC information, to form a plurality of data frames each including the data unit and the ECC for the data unit.

Abstract: According to one embodiment, a memory system includes a memory chip and a controller. The controller is configured to count a first elapsed time from a start of an Erase process when causing the memory chip to execute the Erase process. The controller is configured to cause the memory chip to interrupt the Erase process after the first elapsed time exceeds a threshold value.

Abstract: According to at least one embodiment, a storage apparatus reads first sector data and a first error correcting code. The storage apparatus performs first decoding for the read first sector data using the read first error correcting code. The storage apparatus stores an error correction result by the first decoding. The storage apparatus performs second decoding for decoding-data associated with a second error correcting code using the second error correcting code. The storage apparatus transfers the second error correcting code and the decoding-data via the first buffer storing the error correction result.

Abstract: A storage device includes a memory having one or more storage regions each of which is assigned a physical address, and a controller having a writing control circuit configured to write data that is divided into a plurality of data units into logical storage positions, at least one of which is associated with two storage regions of the memory, and a conversion unit configured to perform a conversion process on a logical address of the logical storage position that is associated with two storage regions of the memory to generate physical addresses corresponding to the two storage regions of the memory.

Abstract: A system (10) for forming and maintaining a biological tissue by which a biological tissue can be artificially formed by culturing cells, which comprises a pulse pump (12), a circulation pathway (13) having such a circuit structure as allowing a liquid cell culture medium discharged from the pulse pump (12) to return into the pulse pump (12), and a cell culture section (14A) and a gas exchange section (14B) provided along the circulation pathway (13). The cell culture section (14A) holds a cell holder (H) in such a manner to form a first channel wherein the liquid cell culture medium flowing in the circulation pathway (13) passes through the cell holder (H) and returns into the circulation pathway (13) and a second channel wherein the liquid cell culture medium flowing in the circulation pathway (13) passes outside the cell holder (H) and returns into the circulation pathway thereby bringing about a difference in pressure between the liquid cell culture medium passing through the respective channels.

Abstract: According to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.

Abstract: According to at least one embodiment, a storage apparatus reads first sector data and a first error correcting code. The storage apparatus performs first decoding for the read first sector data using the read first error correcting code. The storage apparatus stores an error correction result by the first decoding. The storage apparatus performs second decoding for decoding-data associated with a second error correcting code using the second error correcting code. The storage apparatus transfers the second error correcting code and the decoding-data via the first buffer storing the error correction result.

Abstract: Disclosed is a method whereby a narrowed part similar to an actual lesioned blood vessel can be easily obtained. A mold (10) comprises first and second molded members (16, 17) having inner spaces (29, 40, 57) passing through in the axial direction and an axial member (18) detachably inserted through the individual inner spaces (29, 40, 57) of the individual molded members (16, 17). The molded members (16, 17) have tapered front parts (27, 27) respectively. In the state of facing the front ends (20) of the tapered front parts (27) to each other and thus forming a concave (12), the axial member (18) is attached. A first material (75) made of a mixed material comprising calcium carbonate or the like and silicone or the like is applied to the concave (12). A second material (76) such as silicone is applied to the entire outer periphery of the mold (10). After hardening the materials (75, 76), the mold (10) is withdrawn by detaching the axial member (18) and dividing the concave (12).

Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

Abstract: It is intended to provide an endurance test apparatus whereby the behaviors of a vessel caused by a biomechanical burden can be simulated using a relatively simple constitution so that the endurance of a medical instrument (for example, a stent or an artificial vessel after anastomosis) can be tested in a similar state to an actual vessel, and an endurance test method therefor. Namely, an endurance test apparatus (10) comprises a simulated vessel (31) made of an elastic body, first and second holding members (32, 33) respectively supporting the both ends in the axial direction of the simulated vessel (31) and making the both ends relatively rotatable and interval-adjustable, and first and second motors (14, 15) operating these holding members (32, 33). The simulated vessel (31) is supported by the first and second holding members (32, 33) in a state stretched from its inherent length under a tensile force.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals.

Abstract: According to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.