Patents by Inventor Kiyotaka Tsukada

Kiyotaka Tsukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110121448
    Abstract: The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 26, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Kiyotaka TSUKADA, Tetsuya Muraki, Atsunari Yamashita, Yoshitomo Tomida
  • Publication number: 20110121450
    Abstract: A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 26, 2011
    Applicant: IBIDEN CO., LTD.
    Inventors: Kiyotaka Tsukada, Tetsuya Muraki, Atsunari Yamashita, Yoshitomo Tomida
  • Patent number: 7943861
    Abstract: A composite layer composed of an Ni layer 72 and a Pd layer 73 is formed on a solder pad 77U, and a solder 76? on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by means of thermal stress.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: May 17, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Publication number: 20110080714
    Abstract: A circuit board comprises a first conductive post for electrically connecting to the first electrode of the semiconductor device, a first metal plate connecting to the first conductive post, a second conductive post for electrically connecting to the second electrode of the semiconductor device, a second metal plate connecting to the second conductive post, a third conductive post for electrically connecting to the third electrode of the semiconductor device, and a third metal plate connecting to the third conductive post.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 7, 2011
    Applicant: IBIDEN CO., LTD
    Inventors: Kiyotaka Tsukada, Tetsuya Muraki
  • Patent number: 7832098
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 16, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 7786389
    Abstract: A flexible printed wiring board includes a first conductor layer in the element mounting part adjacent to the top surface of the wiring board; a second conductor layer in the element mounting part adjacent to the bottom surface of the wiring board; and a third conductor layer between the first conductor layer and the second conductor layer, wherein the first and third conductor layers extend through and beyond the bending part, and the second conductor layer is absent in the bending part.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: August 31, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Kiyotaka Tsukada, Terumasa Ninomaru, Masaki Kizaki
  • Patent number: 7765692
    Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 3, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
  • Publication number: 20100027228
    Abstract: A semiconductor device includes wiring boards each having an insulating board, conductor circuits and through-holes, the insulating board having top and bottom surfaces, the conductor circuits formed on the top and bottom surfaces, the through holes penetrating the insulating board and electrically connecting the conductor circuits of the top and bottom surfaces; conductor posts each having flange, head and leg portions, the flange portion having first and second surfaces and having an external diameter larger than that of the through-hole, the head portion protruding from the first surface, the leg portion protruding from the second surface; and electronic components each having an electrode formed on one or more surfaces and connected to the leg portion. The head portion is inserted until the first surface of the flange portion comes into contact with the bottom surface of the wiring board and electrically connected at an inner wall of the through-hole.
    Type: Application
    Filed: July 27, 2009
    Publication date: February 4, 2010
    Applicant: IBIDEN CO., LTD.
    Inventors: Kiyotaka TSUKADA, Toshihiro NOMURA, Daisuke MINOURA
  • Publication number: 20090285980
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Application
    Filed: June 30, 2009
    Publication date: November 19, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Tsutomu IWAI, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 7612295
    Abstract: In a printed wiring board, an odd number (n) of conductive layers (11-13) and insulating layers (21-23) are alternately laminated upon another. The first conductive layer (11) is constituted as a parts connecting layer and the n-th conductive layer (13) is constituted as an external connecting layer which is connected to external connecting terminals (7). The second to (n?1)-th conductive layers (12) are constituted as current transmitting layers for transmitting internal currents. The surface of the n-th conductive layer (13) is coated with the outermost n-th insulating layer (23) in a state where the external connecting terminals (7) are exposed on the surface. It is preferable to constitute the initial insulating layers of a glass-cloth reinforced prepreg and the external insulating layers of a resin.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Masaru Takada, Hisashi Minoura, Kiyotaka Tsukada, Hiroyuki Kobayashi, Mitsuhiro Kondo
  • Patent number: 7594320
    Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: September 29, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
  • Publication number: 20090236128
    Abstract: A multilayer printed wiring board is manufactured by a method in which a core substrate is provided, an insulation layer including a thermosetting resin material is formed over the core substrate, an uncured resin layer including a thermoplastic resin material is placed on the insulation layer, the uncured resin layer is cured to form a resin complex layer including a resin complex comprising the thermosetting resin material and the thermoplastic resin material, and a conductive circuit is formed over the resin complex layer.
    Type: Application
    Filed: March 19, 2009
    Publication date: September 24, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Kiyotaka Tsukada, Takamichi Sugiura
  • Publication number: 20090229868
    Abstract: A printed wiring board is manufactured by a method in which a core substrate having an insulation substrate and a conductive circuit formed on the insulation substrate is provided. An inner insulation layer is formed on the core substrate, and a surface of the inner insulation layer is treated to form a roughened portion on the surface. An outer insulation layer including a reinforcing material is formed on the surface of the inner insulation layer having the roughened portion.
    Type: Application
    Filed: January 27, 2009
    Publication date: September 17, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: KIYOTAKA TSUKADA, Takamichi Sugiura
  • Patent number: 7568922
    Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: August 4, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Takahiro Yamashita, Hiroyuki Watanabe, Kiyotaka Tsukada, Michio Ido, Morio Nakao
  • Patent number: 7552531
    Abstract: A method of producing a printed wiring board comprising innerlayer conductor circuits among insulating layers and blind via-holes formed by irradiating laser beams from the outermost surface of the insulating layer toward the innerlayer conductor circuit. A central portion of the innerlayer conductor circuit contains a previously formed opening hole located at the bottom of the blind via-hole. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits and the blind via-holes.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: June 30, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Masaru Takada, Kiyotaka Tsukada, Hiroyuki Kobayashi, Hisashi Minoura, Yoshikazu Ukai, Mitsuhiro Kondo
  • Publication number: 20090019693
    Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.
    Type: Application
    Filed: September 25, 2008
    Publication date: January 22, 2009
    Applicant: IBIDEN CO., LTD
    Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
  • Patent number: 7453702
    Abstract: A printed wiring board comprises the insulating layer 11 (12); at least one resistance element 311 (312) comprising a metal as a main component has 0.5 to 5 ?m of a roughened surface in an arithmetic means height in the one surface, in ?Z direction, and 5% to 50% of the arithmetic mean height in average thickness, which is embedded close to a surface on one side of the insulating layer 11 and a conductive pattern wired surface is composed of the one surface of the resistance element and the one side of the insulating layer 11; and the conductive pattern 351 (352), arranged on the conductive pattern wired surface, is connected to the terminal of the resistance element 311 (312). With this structure, it is provided the printed wiring board comprising the resistance element having an accurate and stable resistance value in a broader resistance value range.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: November 18, 2008
    Assignee: Ibiden Co., Ltd.
    Inventors: Kiyotaka Tsukada, Toshimasa Iwata, Terumasa Ninomaru, Takamichi Sugiura
  • Publication number: 20080264681
    Abstract: A composite layer composed of an Ni layer and a Pd layer is formed on a solder pad, and a solder on the composite layer is composed of a solder containing no lead. Because a Pd layer (palladium layer) reduces phenomenons such as repellency of the solder, adhesiveness with the solder can be enhanced. Because a Pd layer has a higher degree of rigidity than a gold layer, thermal stress is absorbed into the Pd layer and buffered so as to reduce the degree of transmission of stress to the solder bump, or to the solder layer, by thermal stress.
    Type: Application
    Filed: March 15, 2005
    Publication date: October 30, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Tsutomu Iwai, Yoshihiro Kodera, Shinya Maeda, Hiroyuki Watanabe, Kazunari Suzuki, Kiyotaka Tsukada
  • Patent number: 7415761
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 26, 2008
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080189943
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: April 7, 2008
    Publication date: August 14, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda