Patents by Inventor Klaus-Dieter Ufert

Klaus-Dieter Ufert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8492810
    Abstract: Method of fabricating an integrated electronic circuit with programmable resistance cells, which comprises providing a substrate; forming an inert electrode; forming a solid electrolyte on the inert electrode; forming an interlayer on the solid electrolyte, the interlayer comprising an active electrode material and nitrogen; and forming an active electrode on the interlayer, the active electrode comprising the active electrode material.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: July 23, 2013
    Assignee: Qimonda AG
    Inventors: Wolfgang Raberg, Klaus-Dieter Ufert
  • Patent number: 8063394
    Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: November 22, 2011
    Assignee: Qimonda AG
    Inventors: Dieter Andres, Rainer Bruchhaus, Ulrike Gruening-Von Schwerin, Ulrich Klostermann, Franz Kreupl, Michael Kund, Petra Majewski, Christian Ruester, Bernhard Ruf, Ralf Symanczyk, Klaus-Dieter Ufert
  • Patent number: 8062694
    Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 22, 2011
    Assignee: Adesto Technology Corporation
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 8030637
    Abstract: An information storage element has a carbon storage material including hexagonally bonded carbon and tetrahedrally bonded carbon. The information is formed by a changeable ratio of hexagonally bonded carbon and tetrahedrally bonded carbon.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: October 4, 2011
    Assignee: Qimonda AG
    Inventor: Klaus-Dieter Ufert
  • Patent number: 7983068
    Abstract: An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the switching layer, the positive temperature coefficient layer having a resistance that increases in response to an increase in temperature.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: July 19, 2011
    Assignee: Qimonda AG
    Inventor: Klaus-Dieter Ufert
  • Patent number: 7894253
    Abstract: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Michael Kund, Klaus-Dieter Ufert
  • Publication number: 20110037014
    Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Applicant: ADESTO TECHNOLOGY CORPORATION
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 7829134
    Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: November 9, 2010
    Assignee: Adesto Technology Corporation
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 7787279
    Abstract: An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: August 31, 2010
    Assignee: Qimonda AG
    Inventors: Thomas D. Happ, Cay-Uwe Pinnow, Ralf Symanczyk, Klaus-Dieter Ufert
  • Patent number: 7749805
    Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 6, 2010
    Assignee: Qimonda AG
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Patent number: 7741630
    Abstract: An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: June 22, 2010
    Assignee: Qimonda AG
    Inventors: Klaus-Dieter Ufert, Josef Willer
  • Patent number: 7718537
    Abstract: A method for manufacturing CBRAM switching elements and CBRAM semiconductor memories with improved switching characteristics so as to remove superfluous, weak, cluster-like, or unbound selenium at the surface of a GeSe layer is solved by the present invention in that, after the generation of an active matrix material or GeSe layer, respectively, a reactive sputter etching process is performed in which the surface layer of the active matrix material or GeSe layer, respectively, is removed at least partially so as to modify the surface structure thereof.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: May 18, 2010
    Assignee: Qimonda AG
    Inventor: Klaus-Dieter Ufert
  • Publication number: 20100084741
    Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 8, 2010
    Inventors: Dieter Andres, Rainer Bruchhaus, Ulrike Gruening-Von Schwerin, Ulrich Klostermann, Franz Kreupl, Michael Kund, Petra Majewski, Christian Ruester, Bernhard Ruf, Ralf Symanczyk, Klaus-Dieter Ufert
  • Patent number: 7655939
    Abstract: A nonvolatile memory cell, a memory device and a corresponding production method are disclosed. In one embodiment, a memory material region is in this case provided as memory element between a first electrode device and a second electrode device. The memory material region can be activated by means of at least one species. The memory material region is formed with or from a nanostructure.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: February 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Klaus-Dieter Ufert
  • Patent number: 7649242
    Abstract: A programmable resistive memory cell comprising a lower electrode, a programmable resistance layer, and an upper electrode, wherein a lower mask is arranged between the lower electrode and the programmable resistance layer and an upper mask is arranged between the programmable resistance layer and the upper electrode, and wherein the lower mask and the upper mask comprise current-inhibiting regions.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: January 19, 2010
    Assignee: Infineon Technologies AG
    Inventor: Klaus-Dieter Ufert
  • Publication number: 20090272958
    Abstract: An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than one bit of information in the resistive memory element.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: Klaus-Dieter Ufert, Josef Willer
  • Patent number: 7613028
    Abstract: A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: November 3, 2009
    Assignee: Infineon Technologies AG
    Inventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
  • Publication number: 20090200535
    Abstract: An integrated circuit including a memory element is described. The memory element includes a solid electrolyte layer that includes a matrix material having a metal dissolved therein, and a dopant distributed in the matrix material, the dopant competing with the metal to bind with elements of the matrix material at a crystallization temperature so that at least a portion of the metal in the matrix material remains unbound, to increase the temperature stability of the memory element.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 13, 2009
    Inventor: Klaus-Dieter Ufert
  • Publication number: 20090200533
    Abstract: An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventors: Klaus-Dieter Ufert, Josef Willer
  • Publication number: 20090201716
    Abstract: An integrated circuit including a memory element and method for manufacturing the integrated circuit are described. In some embodiments, the memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state, and a positive temperature coefficient layer in thermal contact with the switching layer, the positive temperature coefficient layer having a resistance that increases in response to an increase in temperature.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 13, 2009
    Inventor: Klaus-Dieter Ufert