Abstract: A nonvolatile memory cell, a memory device and a corresponding production method are disclosed. In one embodiment, a memory material region is in this case provided as memory element between a first electrode device and a second electrode device. The memory material region can be activated by means of at least one species. The memory material region is formed with or from a nanostructure.

Abstract: In a method for fabricating a nonvolatile memory element a substrate is provided, a nanomask structure is fabricated on the substrate and a self-assembled monolayer of an organic memory molecule is grown on the substrate on a region not covered by the nanomask structure. A surface of the substrate is patterned by means of an electrode beam in order to form regions with organic memory molecules and regions without organic memory molecules and a top contact is applied to the monolayer formed from the organic memory molecules and the nanomask.

Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Abstract: A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.

Abstract: A method for fabricating a resistively switching memory cell is provided. The method includes the following steps: depositing a first electrode, applying a layer of a chalcogenide compound to the first electrode, applying a layer of silver or copper, and operating a noble gas plasma in a back-sputtering mode in order to effect silver or copper diffusion into the layer of the chalcogenide compound. Optionally, and if appropriate, further layers for the second electrode are then deposited.

Abstract: A resistive memory element for reversibly switching between a high-resistance OFF state and a low-resistance ON state includes a reactive electrode, an inert electrode and a solid electrolyte arranged between the two electrodes. The resistive memory element further includes a nanomask structure arranged in the solid electrolyte, in particular at the inert electrode, where the nanomask structure is provided with openings through which the solid electrolyte makes contact with the inert electrode.

Abstract: A nonvolatile memory element in a semiconductor structure comprises at least two contacts, of which one comprises silicon, and a monolayer of conductive organic molecules producing a conductive connection between the two contacts. The organic molecule comprise alternating ethynyl and aryl groups and have at least one group selected from among benzonitrile, phenylacetonitrile, benzoylacetonitrile, benzoyl cyanide by means of which the molecule bonds via the cyano group to the silicon contact at the end of the molecule.

Abstract: Provides a double gate memory cell having a silicon substrate with an active region having a channel region and source/drain regions, the active region forming a ridgelike fin with at least the channel region. A tunnel oxide layer is formed at least partly on the surface of the ridgelike fin of the active region. A floating gate for storing electrical charges is formed at least partly on the surface of the tunnel oxide layer. An intergate insulator layer made of a dielectric material is formed at least partly on the surface of the floating gate. A control gate is formed at least partly on the surface of the intergate layer, the tunnel oxide layer including an amorphous silicon dioxide/titanium dioxide mixed oxide.

Abstract: A nonvolatile memory cell including a substrate, a first electrode and a second electrode, and an active layer between the first and second electrodes. The active layer includes a self-assembled monolayer of an organic compound, and the second electrode is constructed from carbon-containing materials.

Abstract: A non-volatile, resistively switching memory cell is disclosed. In one embodiment, the memory cell has a first electrode, a second electrode and a solid electrolyte, which is arranged such that it makes contact between the electrodes, and is composed of an amorphous or partially amorphous, non-oxidic matrix and a metal which is distributed in the amorphous or partially amorphous, non-oxidic matrix and whose cations migrate to the cathode in the amorphous or partially amorphous, non-oxidic matrix under the influence of an electrical voltage, wherein the solid electrolyte contains one or more further metallic materials for stabilization of the amorphous state of the matrix.

Abstract: The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching voltages at low switching times and achieves a great number of switching cycles at good temperature stability is solved by the present invention with a semiconductor memory whose memory cells comprise at least one silicon matrix material layer with open or disturbed nanocrystalline or amorphous network structures and structural voids which has a resistively switching property between two stable states, utilizing the ion drift in the silicon matrix material layer. The memory concept suggested in the present invention thus offers an alternative to the flash and DRAM memory concepts since it is not based on the storing of charges, but on the difference of the electric resistance between two stable states that are caused by the mobility of ions in the amorphous silicon matrix material with an externally applied electric field.

Abstract: A method for manufacturing CBRAM switching elements and CBRAM semiconductor memories with improved switching characteristics so as to remove superfluous, weak, cluster-like, or unbound selenium at the surface of a GeSe layer is solved by the present invention in that, after the generation of an active matrix material or GeSe layer, respectively, a reactive sputter etching process is performed in which the surface layer of the active matrix material or GeSe layer, respectively, is removed at least partially so as to modify the surface structure thereof.

Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.

Abstract: The present invention relates to a switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.

Abstract: A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between a first electrode device and a second electrode device. Furthermore, the space or region of the contact recess which is not taken up by the material region of the storage element has been or is made substantially electrically insulating.

Abstract: A solar module has a thin-film structure applied on an aluminum substrate, with the back electrode insulated from the electrically conductive aluminum substrate by an electrically insulating oxide layer. The aluminum substrate can be an aluminum facade element or can be joined to an aluminum facade element. For producing the insulating oxide layer, a known method for the manufacture of electrically conductive oxide electrodes composed of zinc oxide is utilized in a form modified to produce the solar module.