Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Abstract: Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.

Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Abstract: A method for testing a memory includes performing an error correction code check (ECC check) on user data stored in the memory, inverting the user data stored in the memory, performing a further ECC check on the inverted user data stored in the memory, and inverting the inverted user data stored in the memory for restoring the user data in the memory.

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).

Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

Abstract: A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract: A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error detection code (C) or a code word that is inverted in a subset (M) of bits in the memory (11) at a memory location and to read out a data word from the memory (11) from the memory location. The error detection circuit (12) is designed, for the case where a control signal present assumes a first value, to indicate a memory error if the data word is not a code word of the error detection code (C).

Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

Abstract: A method for testing a memory includes performing an error correction code check (ECC check) on user data stored in the memory, inverting the user data stored in the memory, performing a further ECC check on the inverted user data stored in the memory, and inverting the inverted user data stored in the memory for restoring the user data in the memory.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.