Abstract: The invention relates to an opaque, white film with a thickness of from 10 to 500 &mgr;m whose principal constituent is a crystallizable thermoplastic. The film comprises at least barium sulfate and at least one optical brightener. The barium sulfate and/or the optical brightener are incorporated directly into the crystallizable thermoplastic or are fed as a masterbatch during film production. At least one surface of the film bears a functional coating with a thickness of from 5 to 100 nm, in order to confer on the film surface an additional function such as sealability, printability, metallizability, sterilizability, antistatic properties, aroma barrier properties or improved adhesion to materials which would not adhere to the film surface without the coating, for example photographic emulsions.

Abstract: A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Abstract: The present application relates to a white, biaxially oriented, flame-retardant polyester film with at least one base layer which comprises, based on the weight of the base layer, from 2 to 60% by weight of a cycloolefin copolymer (COC), where the glass transition temperature of the COC is within the range from 70 to 270 ° C. The film also comprises from 0.5 to 30% by weight of flame retardant, based on the weight of the layer comprising the flame retardant. The film of the invention is suitable for packing foods or other consumable items which are sensitive to light and/or to air, or for use in industry, e.g. in the production of hot-stamping foils or as a label film, or for image-recording papers, printed sheets or magnetic recording cards.

Abstract: The present invention relates to an opaque, white UV-resistant low-flammability film with a thickness of from 10 to 500 &mgr;m whose principal constituent is a crystallizable thermoplastic. It also comprises at least barium sulfate, at least one UV stabilizer and at least one optical brightener. The barium sulfate and/or the optical brightener and/or the UV stabilizer here is either incorporated directly into the thermoplastic when the polymer is prepared or fed as a masterbatch during film production.

Abstract: A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Abstract: Prefetching data to a low level memory of a computer system is accomplished utilizing an instruction location indicator related to an upcoming instruction to identify a next data prefetch indicator and then utilizing the next data prefetch indicator to locate the corresponding prefetch data within the memory of the computer system. The prefetch data is located so that the prefetch data can be transferred to a primary cache where the data can be quickly fetched by a processor when the upcoming instruction is executed. The next data prefetch indicator is generated by carrying out the addressing mode function that is embedded in an instruction only when the addressing mode of the instruction is a deterministic addressing mode such as a sequential.

Abstract: The microprocessor device has a central processing unit in which the instructions that are stored in a program memory are converted into arithmetic or logical combinations for controlling the different components of the microprocessor. A data and/or control line bus enables data transfer and access to CPU-internal and/or peripheral-bound special function registers, which are assigned to the central processing unit. A coherent memory block with memory cells of the random access type is assigned to the central processing unit through the data and/or control line bus. The memory block has a dedicated address decoder and bus driver circuit, and has a first, arbitrarily usable and/or accessible memory area and a second, peripheral-independent and directly addressable memory area. The memory block is assigned an enable device which disables or enables the output of data contents from the second memory area onto the data and/or control line bus.

Abstract: An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

Abstract: An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.