Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Abstract: In an embodiment, an electronic component includes a high-voltage depletion mode transistor including a current path coupled in series with a current path of a low-voltage enhancement mode transistor, a diode including an anode and a cathode, and a die pad. A rear surface of the high-voltage depletion mode transistor is mounted on and electrically coupled to the die pad. A first current electrode of the low-voltage enhancement mode transistor is mounted on and electrically coupled to the die pad. The anode of the diode is coupled to a control electrode of the high-voltage depletion mode transistor, and the cathode of the diode is mounted on the die pad.

Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.

Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.

Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.

Abstract: A device includes a leadframe having a diepad and leads, a compound semiconductor chip arranged over a first surface of the diepad and including gate, source electrode and drain electrodes, and an encapsulation material covering the compound semiconductor chip and diepad. A second surface of the diepad opposite the first surface is exposed from the encapsulation material. The device also includes a first lead of the leadframe electrically coupled to the gate electrode, a second lead of the leadframe electrically coupled to the source electrode, a third lead of the leadframe electrically coupled to the source electrode, and a fourth lead of the leadframe electrically coupled to the drain electrode. The third lead is configured to provide a sensing signal representing an electrical potential of the source electrode to a gate driver circuit. The gate driver circuit is configured to drive the gate electrode based on the sensing signal.

Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

Abstract: The disclosure is directed to techniques to evenly distribute current in interdigited leadframes by decoupling current between interdigited pads. The leadframe may use a perpendicular structure between the leadframe conductive pads and the lead traces. The perpendicular structure provides a short path for the current to travel from electrode pad openings on a device to the lead traces carrying current to other portions of a circuit. The conductive pad may be parallel to the electrode pad opening to lower spreading resistance. In an example of a transistor, the transistor may have two or more electrode pads for every current carrying node. Therefore, several electrode pads may have the same node, such as the source or drain of the device. For example, two or more source pads may be connected though the leadframe to evenly distribute the current and decouple the current from a single transistor.

Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.

Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.

Abstract: A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

Abstract: In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant.

Abstract: A device includes a compound semiconductor chip having a control electrode, a first load electrode and a second load electrode. A first lead is electrically coupled to the control electrode, a second lead is electrically coupled to the first load electrode, and a third lead is electrically coupled to the first load electrode. The third lead is configured to provide a sensing signal from the first load electrode, the sensing signal being based on a physical parameter of the compound semiconductor chip. The control electrode is configured to receive a control signal based on the sensing signal. A fourth lead is electrically coupled to the second load electrode.

Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Abstract: In an embodiment, an electronic component includes a compound semiconductor transistor device having a first current electrode, a second current electrode and a control electrode, a die pad, a first lead, a second lead and a third lead. The first lead, the second lead and the third lead are spaced at a distance from the die pad. The control electrode is coupled to the first lead, the first current electrode is coupled to the die pad and the second current electrode is coupled to the second lead. The third lead is coupled to the compound semiconductor transistor device and provides a source sensing functionality.

Abstract: A packaged semiconductor includes an electrically insulating encapsulant having opposite facing first and second planar sides. A thermally conductive substrate is partially embedded in the encapsulant such that an outer side of the substrate is exposed at the first side of the encapsulant and an inner side of the substrate is contained within the encapsulant. A GaN based power semiconductor device is completely embedded in the encapsulant and includes: a main side having electrically conductive device terminals, and a rear side that faces away from the main side and is mounted on the inner side the substrate. A plurality of electrically conductive leads is partially embedded in the encapsulant and electrically connected to the device terminals. Vertical portions of the leads extend away from the substrate towards the second side of the encapsulant.

Abstract: Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material.

Abstract: An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encapsulation body, a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip, and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. The electrically insulating layer is completely separated from the semiconductor chip.