Abstract: In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead.

Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.

Abstract: An electronic module includes a semiconductor package, a heat spreader attached to the semiconductor package and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package.

Abstract: An electronic device includes multiple semiconductor chips in a single housing. Such semiconductor chips may comprise different semiconductor materials, for example they may comprise GaN. Using bonding clips instead of bonding wires is an efficient way of connecting such semiconductor chips to a substrate.

Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.

Abstract: In an embodiment, a semiconductor device includes a lateral transistor device having an upper metallization layer. The upper metallization layer includes n elongated pad regions. Adjacent ones of the n elongated pad regions are coupled to different current electrodes of the lateral transistor device. The n elongated pad regions bound n-1 active regions of the lateral transistor where n?3.

Abstract: In an embodiment, an electronic component includes a high-voltage depletion mode transistor including a current path coupled in series with a current path of a low-voltage enhancement mode transistor, a diode including an anode and a cathode, and a die pad. A rear surface of the high-voltage depletion mode transistor is mounted on and electrically coupled to the die pad. A first current electrode of the low-voltage enhancement mode transistor is mounted on and electrically coupled to the die pad. The anode of the diode is coupled to a control electrode of the high-voltage depletion mode transistor, and the cathode of the diode is mounted on the die pad.

Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract: A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad.

Abstract: Various embodiments provide a power transistor arrangement, which may include a carrier including at least a main region, a first terminal region and a second terminal region being electrically isolated from each other; a first power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the main region of the carrier such that its first power electrode is facing towards and is electrically coupled to the main region of the carrier; a second power transistor having a control electrode, a first power electrode and a second power electrode, and being arranged on the terminal regions of the carrier such that its control electrode and its first power electrode are facing towards the terminal regions, and having its control electrode being electrically coupled to the first terminal region and its first power electrode being electrically coupled to the second terminal region.

Abstract: A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier.

Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.

Abstract: An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Abstract: A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.

Abstract: In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead.