Patents by Inventor Kohei Masuda

Kohei Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8713231
    Abstract: To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Publication number: 20140023855
    Abstract: Core/shell type tetragonal titanium oxide particles consisting of a nanosized core of tetragonal titanium oxide having tin and manganese incorporated in solid solution and a shell of silicon oxide around the core are dispersed in an aqueous dispersing medium. The cores and the core/shell type titanium oxide particles have an average particle size of ?30 nm and ?50 nm, respectively. The amount of tin or manganese in solid solution is to provide a molar ratio Ti/Sn or Ti/Mn between 10 and 1,000.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 23, 2014
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Kohei MASUDA, Koichi HIGUCHI, Hisatoshi KOMORI, Manabu FURUDATE, Tomohiro INOUE, Yoshitsugu EGUCHI
  • Publication number: 20130336428
    Abstract: In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: Panasonic Corporation
    Inventors: Shinichiro NISHIOKA, Yoshihide KOMATSU, Hiroshi SUENAGA, Kohei MASUDA
  • Patent number: 8605776
    Abstract: A comparator circuit compares a test pattern generated by a test pattern generator circuit, with a test pattern transmitted to a memory card and returned from the memory card. A control circuit determines a bandwidth corresponding to frequency components correctly transmitted between a host apparatus and the memory card, based on the returned test pattern, and selects an encoding method requiring a maximum available bandwidth. The control circuit generates a notification message indicating the selected encoding method, and encodes the notification message using the selected encoding method, and transmit the encoded notification message to the memory card. The control circuit establishes communication between the host apparatus and the memory card, when receiving a response message including an acknowledgement to the notification message, from the memory card.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: December 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Kohei Masuda, Hiroshi Tanaka, Tsuyoshi Ikushima, Takeshi Nakayama
  • Patent number: 8548070
    Abstract: In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Patent number: 8548069
    Abstract: A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: October 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Kohei Masuda, Yoshihide Komatsu, Masashi Suzuki
  • Publication number: 20130251017
    Abstract: A comparator circuit compares a test pattern generated by a test pattern generator circuit, with a test pattern transmitted to a memory card and returned from the memory card. A control circuit determines a bandwidth corresponding to frequency components correctly transmitted between a host apparatus and the memory card, based on the returned test pattern, and selects an encoding method requiring a maximum available bandwidth. The control circuit generates a notification message indicating the selected encoding method, and encodes the notification message using the selected encoding method, and transmit the encoded notification message to the memory card. The control circuit establishes communication between the host apparatus and the memory card, when receiving a response message including an acknowledgement to the notification message, from the memory card.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicant: Panasonic Corporation
    Inventors: Hiroshi SUENAGA, Kohei MASUDA, Hiroshi TANAKA, Tsuyoshi IKUSHIMA, Takeshi NAKAYAMA
  • Publication number: 20130242513
    Abstract: An electronic device includes a conductor plate, a circuit board placed with a distance to a surface of the conductor plate, a connector provided on the circuit board, a flexible cable having one end connected to the connector and laid down along the surface of the conductor plate, and a cable holding member which includes a sloped holding surface for holding at least part of a portion of the flexible cable ranging from the connector to the surface of the conductor plate and which is electrically connected to the conductor plate.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 19, 2013
    Applicant: Panasonic Corporation
    Inventors: Kohei MASUDA, Osamu SHIBATA, Yoshiyuki SAITO
  • Publication number: 20120112784
    Abstract: An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.
    Type: Application
    Filed: April 13, 2011
    Publication date: May 10, 2012
    Inventors: Kohei Masuda, Osamu Shibata, Hiroshi Suenaga, Yoshiyuki Saito
  • Publication number: 20120021640
    Abstract: A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside.
    Type: Application
    Filed: April 26, 2010
    Publication date: January 26, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kohei Masuda, Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito
  • Publication number: 20110280322
    Abstract: A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
    Type: Application
    Filed: October 13, 2010
    Publication date: November 17, 2011
    Inventors: Hiroshi Suenaga, Osamu Shibata, Yoshiyuki Saito, Kohei Masuda, Yoshihide Komatsu, Masashi Suzuki
  • Publication number: 20110268198
    Abstract: In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
    Type: Application
    Filed: November 1, 2010
    Publication date: November 3, 2011
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda
  • Publication number: 20110241432
    Abstract: To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.
    Type: Application
    Filed: November 1, 2010
    Publication date: October 6, 2011
    Inventors: Shinichiro Nishioka, Yoshihide Komatsu, Hiroshi Suenaga, Kohei Masuda