Patents by Inventor Koichi Fujisaki
Koichi Fujisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9304578Abstract: A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.Type: GrantFiled: September 5, 2013Date of Patent: April 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
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Publication number: 20160085292Abstract: According to an embodiment, an electronic device includes functional modules and converters. A processor includes a memory storing state information on the state of the processor. Each converter converts the power-supply voltage to a rated voltage for functional modules, and supplies the rated voltage to at least one functional module. When the processor switches to the standby state, a controller stops the supply of the rated voltages to the functional modules except a state holding unit, a receiving unit, and the controller; and stops the operations of the converters not connected to the state holding unit, the receiving unit, and the controller. The state holding unit holds the state information before the processor switches to the standby state. The receiving unit receives a return signal representing the trigger for returning from the standby state. The state holding unit, the receiving unit, and the controller are connected to the same converter.Type: ApplicationFiled: September 8, 2015Publication date: March 24, 2016Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
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Patent number: 9288040Abstract: According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N?1.Type: GrantFiled: August 14, 2012Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tsukasa Endo, Yuichi Komano, Koichi Fujisaki, Hideo Shimizu, Hanae Ikeda, Atsushi Shimbo
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Publication number: 20160070333Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.Type: ApplicationFiled: November 2, 2015Publication date: March 10, 2016Inventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
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Publication number: 20160020696Abstract: According to a power system includes a linear regulator, a step-down switching regulator, and a controller. The linear regulator supplies electrical power to a load. The step-down switching regulator supplies electrical power to the load. Based on input voltage of the linear regulator and the step-down switching regulator and based on load current representing electrical current flowing to the load, the controller performs control to supply electrical power to the load from one of the linear regulator and the switching regulator.Type: ApplicationFiled: May 11, 2015Publication date: January 21, 2016Inventors: Akihiro Shibata, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Shiyo Yoshimura
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Patent number: 9207743Abstract: According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.Type: GrantFiled: December 21, 2012Date of Patent: December 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyoshi Haruki, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Yusuke Shirota, Akihiro Shibata, Masaya Tarui, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama
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Publication number: 20150271817Abstract: According to an embodiment, a communication device for dynamically building a network includes a first receiver and a first transmitter. When the communication device attempts to newly join the network, the first receiver waits for reception of a first beacon containing information for joining the network from another communication device already joining the network for a predetermined first period. When the communication device is already joining the network, the first transmitter determines a schedule indicating timings at which a plurality of communication devices already joining the network transmit first beacons so that intervals at which the communication devices transmit the first beacons in the network as a whole do not exceed the first period and transmit the first beacon according to the schedule.Type: ApplicationFiled: March 5, 2015Publication date: September 24, 2015Inventors: Masaya Tarui, Koichi Fujisaki, Junichi Segawa, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Tetsuro Kimura, Tatsunori Kanai
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Publication number: 20150262715Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.Type: ApplicationFiled: March 4, 2015Publication date: September 17, 2015Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
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Publication number: 20150261283Abstract: According to an embodiment, a communication device includes a register and a controller. The register receives data from an external device via an input data line. In a first state in which the communication device is able to receive the data, when a condition in which the data is not sent to the input data line continues for a certain period of time, the controller controls to switch state of the communication device to a second state in which power consumption is less than in the first state.Type: ApplicationFiled: March 5, 2015Publication date: September 17, 2015Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
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Publication number: 20150234752Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Toru KAMBAYASHI, Akihiro KASAHARA, Shinichi MATSUKAWA, Hiroyuki SAKAMOTO, Taku KATO, Hiroshi SUKEGAWA, Yoshihiko HIROSE, Atsushi SHIMBO, Koichi FUJISAKI
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Patent number: 9110667Abstract: According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.Type: GrantFiled: July 11, 2012Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Shirota, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Akihiro Shibata
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Publication number: 20150228047Abstract: A data processing device according to embodiments may comprise: a processor that reconstructs a plurality of update requests for updating at least a part of a display into one or more update requests, or determine that the plurality of the update requests are unnecessary; and an update instruction unit that instructs to execute update processes of the display using the reconstructed one or more update requests.Type: ApplicationFiled: February 6, 2015Publication date: August 13, 2015Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Akihiro Shibata
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Publication number: 20150212572Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.Type: ApplicationFiled: April 13, 2015Publication date: July 30, 2015Inventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
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Patent number: 9053062Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.Type: GrantFiled: June 13, 2014Date of Patent: June 9, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toru Kambayashi, Akihiro Kasahara, Shinichi Matsukawa, Hiroyuki Sakamoto, Taku Kato, Hiroshi Sukegawa, Yoshihiko Hirose, Atsushi Shimbo, Koichi Fujisaki
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Patent number: 9043631Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.Type: GrantFiled: July 24, 2012Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaya Tarui, Koichi Fujisaki, Hiroyoshi Haruki, Tatsunori Kanai, Haruhiko Toyama, Tetsuro Kimura, Junichi Segawa, Yusuke Shirota, Satoshi Shirai, Akihiro Shibata
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Patent number: 8995666Abstract: According to one embodiment, in a key scheduling device, a non-linear transformation unit non-linearly transforms at least one of partial keys resulting from dividing an expanded key. A first linear transformation unit includes first and second circuits. The second circuit linearly transforms the partial key by directly using a transformation result from the non-linear transformation unit. A first storage stores the partial key linearly transformed by the first linear transformation unit. A second linear transformation unit linearly transforms, inversely to the first linear transformation unit, each of partial keys other than the partial key linearly transformed by the second circuit out of the partial keys stored in the first storage, and outputs inversely transformed partial keys. A second storage stores one of inputs to the second circuit. An outputting unit connects the respective inversely transformed partial keys and the input stored in the second storage to be output as a second key.Type: GrantFiled: March 21, 2012Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kawabata, Koichi Fujisaki, Atsushi Shimbo
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Publication number: 20150084892Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.Type: ApplicationFiled: September 11, 2014Publication date: March 26, 2015Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
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Publication number: 20150089261Abstract: According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state.Type: ApplicationFiled: August 27, 2014Publication date: March 26, 2015Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura, Haruhiko Toyama
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Patent number: 8942374Abstract: According to an embodiment, an encryption device includes a symmetric-key operation unit; a division unit; an exclusive OR operation unit; a multiplication unit that performs multiplication on a Galois field; and a control unit that controls the above units. When the input data is divided into blocks, with the predetermined length, and the first mode of operation is designated on a (j?1)-th block, the control unit performs control such that the multiplication unit performs multiplication with a predetermined value based on the (j?1)-th block, performs control such that the exclusive OR operation unit sums a multiplication result and data of a j-th block, and performs control such that the exclusive OR operation unit sums an operation result of the exclusive OR operation unit and an operation result of the multiplication unit on the (j?1)-th block.Type: GrantFiled: August 26, 2011Date of Patent: January 27, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Fujisaki
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Publication number: 20150019895Abstract: According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Inventors: Koichi Fujisaki, Tatsunori Kanai, Tetsuro Kimura, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Akihiro Shibata