Abstract: According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.

Abstract: According to one embodiment, a cryptographic apparatus includes: cryptographic cores (“cores”), an assigning unit, a concatenating unit, and an output controlling unit. If a CTS flag thereof is on, each core encrypts using a symmetric key cipher algorithm utilizing CTS, while using a symmetric key. When an input of a CTS signal is received, the assigning unit assigns first input data to a predetermined core and turns on the CTS flag thereof. The concatenating unit generates concatenated data by concatenating operation data generated during encrypting the first input data, with second input data that is input immediately thereafter. The output controlling unit controls outputting the concatenated data to the predetermined core, outputting first encrypted data obtained by encrypting the concatenated data, and over outputting second encrypted data obtained by encrypting the first input data, and further turns off the predetermined core's CTS flag.

Abstract: According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor.

Abstract: According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Abstract: One embodiment is a computer program product for processing information to obtain an HMAC, comprising: by using a padding circuit, generating first key data by adding 0 with respect to secret key data, setting the secret key data as second key data, or generating third key data by adding 0 with respect to a first digest value, according to comparison result of a second key length and a block length of the hash function, and performing an exclusive OR operation with a second constant with respect to one of the first key data, the second key data, and the third key data to calculate first data; by using a hash calculation circuit, obtaining the first digest value, and obtaining a second digest value, by using a holding circuit, storing the secret key data or the first digest value; and by using a control unit, managing a processing state for calculating the HMAC.

Abstract: According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

Abstract: According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit.

Abstract: According to an embodiment, a control device includes a processor setting unit, a resumption data reading unit, and a resumption processing unit. The processor setting unit is configured to identify, among a plurality of processors included in an information processing system, each of which is connected to one or more memories, a processor connected to a memory storing resumption data for resuming the information processing system and to activate the identified processor, in response to a resumption request for resuming the information processing system from hibernation. The information processing system includes two or more processors each connected with one or more memories. The resumption data reading unit is configured to read the resumption data from the memory that stores the resumption data. The resumption processing unit is configured to resume the information processing system by using the read resumption data.

Abstract: According to an embodiment, an information processing apparatus that includes a processor, has a first control unit, a power storage unit, and a second control unit. The first control unit is configured to control execution of a process by the processor. The power storage unit is configured to store therein power. The second control unit is configured to control reduction of power consumption of the information processing apparatus in a case where there is a process waiting to be executed and an amount of stored power of the power storage unit is equal to or less than a first threshold.

Abstract: A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory.

Abstract: According to one embodiment, a cryptographic processing apparatus is provided with first to fifth units. The first unit mask-converts input data from first temporary mask into first fixed mask (an invariable value in a first linear operation). In an encryption, the third unit performs a nonlinear operation on the mask-converted data and outputs a first result masked with second fixed mask data (an invariable value in a second linear operation). The fourth unit performs the second linear operation and outputs a encryption result masked with second fixed mask data. In a decryption, the second unit performs the first linear operation on the mask-converted data and outputs a second result masked with the first fixed mask. The third unit performs the nonlinear operation and outputs a decryption result masked with the second fixed mask. In encryption/decryptions, the fifth unit converts the mask of the encryption/decryption results into second temporary mask.

Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.

Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.

Abstract: According to an embodiment, a power supply system includes a power storage unit, a changeover unit, and a control unit. The power storage unit is configured to store electric power generated by a power generation unit. The changeover unit is configured to make a changeover between a first state in which a load is connected to the power generation unit and a second state in which the load is connected to the power storage unit but not the power generation unit. The control unit is configured to perform control to make the changeover to the first state when a value obtained by subtracting a first value from a value of the electric power fed from the power generation unit is not less than a value of the electric power fed to the load. Otherwise, the control unit is configured to perform control to make the changeover to the second state.

Abstract: A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.

Abstract: One embodiment is a computer program product for processing information to obtain an HMAC, comprising: by using a padding circuit, generating first key data by adding 0 with respect to secret key data, setting the secret key data as second key data, or generating third key data by adding 0 with respect to a first digest value, according to comparison result of a second key length and a block length of the hash function, and performing an exclusive OR operation with a second constant with respect to one of the first key data, the second key data, and the third key data to calculate first data; by using a hash calculation circuit, obtaining the first digest value, and obtaining a second digest value, by using a holding circuit, storing the secret key data or the first digest value; and by using a control unit, managing a processing state for calculating the HMAC.

Abstract: According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.

Abstract: According to an embodiment, an information processing apparatus includes a processor, a first memory, and a power supply controller. The processor is configured to execute a program. The first memory is configured to store therein the program. The power supply controller is configured to stop supplying a power to the first memory when the processor transitions to an idle state where the processor waits for an interrupt, and start supplying the power to the first memory when the processor receives the interrupt in the idle state. When the processor receives the interrupt in the idle state, the processor executes initialization of the first memory to set the first memory into a state where the first memory is accessible from the processor.

Abstract: One embodiment is an information processing device for obtaining an HMAC, including a padding circuit for generating first key data by adding a first constant with respect to secret key data, setting the secret key data as second key data when the secret key length is equal to the block length, generating third key data by adding the first constant with respect to a first digest value; a hash calculation circuit for obtaining the first digest value; and a control unit for managing a processing state for calculating the HMAC, wherein the hash calculation circuit outputs a first midway progress value when interrupting a calculation process of the first digest value, and resumes the calculation process of the first digest using the first midway progress value when a signal indicating resuming instruction of the calculation process of the first digest value is input to the control unit.