Abstract: The present invention relates to the use of a yellow and/or a red and/or a blue component of disperse dyes for dyeing poly(lactic acid) fibers or poly(lactic acid) based fibers.

Abstract: A first Exclusive OR circuit operates an Exclusive OR between input data and a predetermined random number. An operation circuit performs one operation of encryption and decryption of output data from the first Exclusive OR circuit. A data register circuit, which has a plurality of data hold units, holds data from the operation circuit in one data hold unit of the plurality of data hold units in response to a selection signal, and supplies the data from the one data hold unit to the operation circuit. A second Exclusive OR circuit performs an Exclusive OR between output data from the data register circuit and the random number. The operation circuit recursively performs the one operation of the data from the data register circuit and outputs next data to the data register circuit.

Abstract: A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache memory is provided with a plurality of cache lines that include a tag area storing an address on the main memory, a capacity area storing a capacity value of a cache block, and a cache block. When a read request is executed from the processor to the main memory, the cache controller checks whether the requested data is present in the cache memory or not. A cache capacity determination unit determines a capacity value for the cache block and supplies to a capacity area.

Abstract: An encryption apparatus provided with a Feistel type encryption algorithm includes a function operation unit that operates a non-linear function, and changing unit configured to supply the function operation unit with random data unrelated to an encryption operation result. In this way, a countermeasure can be taken against a DPA attack following the end of an operation by the encryption operation apparatus provided with the Feistel type encryption algorithm.

Abstract: The present invention provides a blue dye mixture which contains the pigments represented by formulae [1], [2], [3], and [4] The present invention also relates to dye mixtures in which there are compounded therewith a yellow dye mixture and/or a red dye mixture. The invention further relates to a method of dyeing polyester-based fibers and dyed polyester-based fibers and dyed polyester-based fiber materials.

Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.

Abstract: A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of output signal lines. The first data is one bit data represented by a combination of bits of the plurality of input signal lines. The second data is one bit data represented by a combination of bits of the plurality of output signal lines.

Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner data is read from a magnetoresistive memory module in both row and column directions.

Abstract: A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.

Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner, data is read from a magnetoresistive memory module in both row and column directions.

Abstract: A calculation apparatus capable of executing any of a first calculating process operation including a first matrix calculation, and a second calculating process operation including a second matrix calculation, includes: a first calculation unit for executing the second matrix calculation; at least one calculation unit other than the first calculation unit, for executing a matrix calculation in parallel to the first calculation unit so as to execute the first matrix calculation; and a logic circuit for performing a logic calculation with respect to a calculation result of the first calculation unit and a calculation result of the other calculation unit. Then, when a calculation result of the first matrix calculation is requested, the calculation apparatus acquires the calculation result from the logic circuit.

Abstract: A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of output signal lines. The first data is one bit data represented by a combination of bits of the plurality of input signal lines. The second data is one bit data represented by a combination of bits of the plurality of output signal lines.

Abstract: An encryption apparatus provided with a Feistel type encryption algorithm includes a function operation unit that operates a non-linear function, and changing unit configured to supply the function operation unit with random data unrelated to an encryption operation result. In this way, a countermeasure can be taken against a DPA attack following the end of an operation by the encryption operation apparatus provided with the Feistel type encryption algorithm.

Abstract: A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction.