Abstract: An electrooptic apparatus substrate and examination method therefor can be provided which can implement an examination without requiring bringing a probe into contact thereto from the outside and with satisfactory measuring accuracy. A substrate 1 of the present invention includes a video line 7 and transmission gate portion 6 through multiple switching elements for writing a first potential signal in multiple pixels through a signal line. The substrate 1 further includes a display data reading circuit portion 4 having a differential amplifier 4a for lowering a lower potential and heightening a higher potential and outputting it to the signal line and a transmission gate port on 6 and video line 7 for reading the first potential signal and a reference second potential signal.

Abstract: In a method for forming a layer using a droplet discharging device that discharges droplets from a plurality of nozzles while relatively moving a surface in a first direction with respect to a head including the plurality of nozzles, the method for forming a layer comprises: a) respectively arranging a first droplet on each of two reference regions on the surface and providing two separate patterns corresponding to the two reference regions; b) fixing the two patterns; c) making the surface lyophilic after fixing the two patterns; and d) arranging a second droplet between the two reference regions and connecting the two patterns after making the surface lyophilic.

Abstract: A droplet ejection head drive method includes (1) associating multiple nozzles with ranks corresponding to weights of droplets ejected from the nozzles, (2) generating drive waveforms for driving actuators of the nozzles and correcting the weights of the droplets to a predetermined weight, for each of the ranks, and (3) supplying the drive waveforms corresponding to the ranks of some of the nozzles selected according to drawing data, to actuators of the selected nozzles and ejecting droplets each having the predetermined weight from the selected nozzles onto a target.

Abstract: In a method for forming a layer using a droplet discharging device that discharges droplets from a plurality of nozzles while relatively moving a surface in a first direction with respect to a head including the plurality of nozzles, the method for forming a layer comprises: a) respectively arranging a first droplet on each of two reference regions on the surface and providing two separate patterns corresponding to the two reference regions; b) fixing the two patterns; c) making the surface lyophilic after fixing the two patterns; and d) arranging a second droplet between the two reference regions and connecting the two patterns after making the surface lyophilic.

Abstract: A method for forming a layer comprises (a) disposing a first droplet to two parts on an underlayer surface so as to form two dot patterns isolated each other on the underlayer surface, (b) fixing the two dot patterns to the underlayer surface, (c) giving lyophilicity with respect to a second droplet to at least the underlayer surface between the two dot patterns, and (d) disposing the second droplet to the underlayer surface between the two dot patterns so as to join the two dot patterns after the step (c).

Abstract: The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.

Abstract: In the semiconductor memory device of the invention, even in the case of generation of a write access request or a refresh request in advance, an access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while a write enable signal supplied from an external device is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller comprises: a refresh timing signal generator, a refresh request signal generator, and a refresh execution signal generator. The refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated. The refresh request signal generator generates the refresh request signal if a difference of the two number of times of signal generation is one or more. The refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.

Abstract: In the semiconductor memory device of the invention, while a write enable signal supplied from an external device is at an active level representing a data writing request, an access control module prohibits start of any of a read access operation, a write access operation, and a refresh operation, even in the case of generation of any one of a read access request, a write access request, and a refresh request. Even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while the write enable signal is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.

Abstract: An external access timing signal becomes active according to changes of the external address. An address latch signal becomes active according to the timing when the external access timing signal becomes active. In a case where the changes of the external address occurs while the address latch signal is active and consequently the external access timing signal becomes active, a refresh arbiter signal does not become active. When the refresh arbiter signal becomes active after the generation of the refresh timing signal, a refresh execution timing signal becomes active according to the change of the refresh arbiter signal. The time period when the address latch signal is active is set to be substantially the same as the preferable activation time period. The time period when the external access timing signal is active is set to be substantially the same as the preferable pre-charge time period.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller can maintain an the activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles. If a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, the word line activation controller can deactivate the activated word line prior to performing the refresh operation.

Abstract: In the semiconductor memory device of the invention, when a write enable signal supplied from an external device changes to an active level representing a data writing request, an access controller triggers execution of a write access operation for a preset time period at a return timing of the write enable signal to an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.

Abstract: In the semiconductor memory device of the invention, even in the case of generation of a write access request or a refresh request in advance, an access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while a write enable signal supplied from an external device is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller comprises: a refresh timing signal generator, a refresh request signal generator, and a refresh execution signal generator. The refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated. The refresh request signal generator generates the refresh request signal if a difference of the two number of times of signal generation is one or more. The refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.

Abstract: In the semiconductor memory device of the invention, while a write enable signal supplied from an external device is at an active level representing a data writing request, an access control module prohibits start of any of a read access operation, a write access operation, and a refresh operation, even in the case of generation of any one of a read access request, a write access request, and a refresh request. Even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while the write enable signal is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks, specifically blocks A to D. During a period in which data read or write operations are being performed in one block, refreshing is performed for the remaining blocks. An ATD signal acts as a trigger for a series of operations during the reading or writing of memory cells. In a burst mode, refreshing is based on the ATD signal.

Abstract: In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.

Abstract: An external access timing signal becomes active according to changes of the external address. An address latch signal becomes active according to the timing when the external access timing signal becomes active. In a case where the changes of the external address occurs while the address latch signal is active and consequently the external access timing signal becomes active, a refresh arbiter signal does not become active. When the refresh arbiter signal becomes active after the generation of the refresh timing signal, a refresh execution timing signal becomes active according to the change of the refresh arbiter signal. The time period when the address latch signal is active is set to be substantially the same as the preferable activation time period. The time period when the external access timing signal is active is set to be substantially the same as the preferable pre-charge time period.