Abstract: A semiconductor device includes a memory cell array which is divided into four blocks, specifically, a block (0), a block (1), a block (2), and a block (3). In this semiconductor device, during a period in which the data read or write is performed in one block, refreshing is executed in all of the other blocks. The block (0) to block (3) are selected by an address signal A0 which is a signal of the least significant bit of the address signals and an address signal A1 which is a signal of the next least significant bit of the address signals. Since the address signal frequently changes as the bit order of the signal decreases, continuous delayed of the refreshing in one block can be prevented.

Abstract: A semiconductor memory device, such as a virtual SRAM, includes a temperature detection module and a temperature characteristic regulation module. The temperature detection module has a temperature sensing element, which includes a specific pn junction area set in a cutoff state out of pn junction areas formed on an identical semiconductor substrate with a memory cell array and outputs a leak current running through the specific pn junction area. The temperature detection module detects a temperature change of the semiconductor memory device in response to the leak current output from the temperature sensing element. The temperature characteristic regulation module regulates a generation period of a refresh timing signal, which is used to determine an execution timing of a refreshing operation in the memory cell array, based on a result of the detection by the temperature detection module.

Abstract: A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for the other blocks. An RF address controller 120 has a function of making logic of a signal RFA18 and a signal RFA19 among refresh address signals RFA8 to RFA19 constant so that only part of each block of the blocks A to D is refreshed in a power saving state.

Abstract: The technique of the present invention sets a time period of a level H between a rise and a fall of an ATD signal (that is, a pulse width of the ATD signal) to be not shorter than a preset allowable address skew range and not longer than a time period between a timing of a rise of the ATD signal, at which the refreshing operation starts, and conclusion of the refreshing operation. This arrangement ensures generation of an appropriate ATD signal even when an address skew occurs in an externally given address.

Abstract: A semiconductor memory device includes: at least one memory cell block including multiple dynamic memory cells arrayed in a matrix; a row address decoder and a column address decoder that select a memory cell in the memory cell block, which is specified by an address including a row address and a column address; an output buffer that causes data to be output from the selected memory cell specified by the address; a preset circuit that presets an output level of the output buffer; and a preset control module that controls an operation of the preset circuit. At every time of outputting data from the memory cell selected by the column address decoder, the output level of the output buffer is preset, prior to output of the data from the selected memory cell by means of the output buffer. This arrangement effectively prevents the potential noise in a power source of the semiconductor memory device.

Abstract: A semiconductor memory device including a first memory cell block and a second memory cell block, both cell blocks having memory cells arranged in a matrix, and a common preamplifier/write driver located between and shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells.

Abstract: In the operation cycle, memory chip 200 initiates a refresh operation in synchronism with an external clock signal CLK after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of a clock signal CLK.

Abstract: The present invention provides a semiconductor device that includes a memory cell array that can be divided into four blocks. During a period in which data is read or written in one of the blocks, refreshing is conducted in all of the other remaining blocks. Also, in a standby state or in an operation state, refreshing for each of the plurality of blocks is performed with time differences provided therebetween, such that the peak current is lowered.

Abstract: The technique of the present invention sets a time period of a level H between a rise and a fall of an ATD signal (that is, a pulse width of the ATD signal) to be not shorter than a preset allowable address skew range and not longer than a time period between a timing of a rise of the ATD signal, at which the refreshing operation starts, and conclusion of the refreshing operation. This arrangement ensures generation of an appropriate ATD signal even when an address skew occurs in an externally given address.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the controller maintains an activated state of a word line without deactivation thereof until the row address changes. In the event of a refresh request when a word line in a certain block is in an activated state, the controller can deactivate the word line, with the proviso that no external access is currently being performed in the block. Where a request for external access to the block is made within a predetermined period after the refresh request, the refresh operation for the block is suspended, and the word line for external access is activated.

Abstract: A semiconductor memory device, such as a virtual SRAM, includes a temperature detection module and a temperature characteristic regulation module. The temperature detection module has a temperature sensing element, which includes a specific pn junction area set in a cutoff state out of pn junction areas formed on an identical semiconductor substrate with a memory cell array and outputs a leak current running through the specific pn junction area. The temperature detection module detects a temperature change of the semiconductor memory device in response to the leak current output from the temperature sensing element. The temperature characteristic regulation module regulates a generation period of a refresh timing signal, which is used to determine an execution timing of a refreshing operation in the memory cell array, based on a result of the detection by the temperature detection module.

Abstract: A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for all the remaining blocks. A refresh cycle in a power saving state is caused to be longer than a refresh cycle in an operating state.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles.

Abstract: A semiconductor device includes a memory cell array which is divided into four blocks, specifically, a block (0), a block (1), a block (2), and a block (3). In this semiconductor device, during a period in which the data read or write is performed in one block, refreshing is executed in all of the other blocks.

Abstract: A semiconductor memory device includes: at least one memory cell block including multiple dynamic memory cells arrayed in a matrix; a row address decoder and a column address decoder that select a memory cell in the memory cell block, which is specified by an address including a row address and a column address; an output buffer that causes data to be output from the selected memory cell specified by the address; a preset circuit that presets an output level of the output buffer; and a preset control module that controls an operation of the preset circuit. At every time of outputting data from the memory cell selected by the column address decoder, the output level of the output buffer is preset, prior to output of the data from the selected memory cell by means of the output buffer.

Abstract: In the operation cycle, memory chip 200 initiates a refresh operation in sync with an ATD signal indicating change of address after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of the ATD signal.

Abstract: The invention provides a semiconductor device that includes a memory cell array that is divided into four blocks. During a period in which data is read or written in one of the blocks, refreshing is conducted in all of the other remaining blocks. An ATD signal triggers a series of operations that are performed when a memory cell is read or written. Refreshing is conducted based on the ATD signal.

Abstract: The present invention provides a method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks, specifically blocks A to D. During a period in which data read or write operations are being performed in one block, refreshing is performed for the remaining blocks. An ATD signal acts as a trigger for a series of operations during the reading or writing of memory cells. In a burst mode, refreshing is based on the ATD signal.

Abstract: A semiconductor memory device includes: a first memory cell block and a second memory cell block, in each of which memory cells are arranged in a matrix; and a common preamplifier/write driver shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells. The common preamplifier/write driver is located between the first memory cell block and the second memory cell block.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the controller maintains an activated state of a word line without deactivation thereof until the row address changes. In the event of a refresh request when a word line in a certain block is in an activated state, the controller can deactivate the word line, with the proviso that no external access is currently being performed in the block. Where a request for external access to the block is made within a predetermined period after the refresh request, the refresh operation for the block is suspended, and the word line for external access is activated.