Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller can maintain an the activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles. If a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, the word line activation controller can deactivate the activated word line prior to performing the refresh operation.

Abstract: The present invention provides a semiconductor device that includes a memory cell array that can be divided into four blocks. During a period in which data is read or written in one of the blocks, refreshing is conducted in all of the other remaining blocks. Also, in a standby state or in an operation state, refreshing for each of the plurality of blocks is performed with time differences provided therebetween, such that the peak current is lowered.

Abstract: A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for all the remaining blocks. A refresh cycle in a power saving state is caused to be longer than a refresh cycle in an operating state.

Abstract: A method of refreshing a semiconductor device such as a VSRAM. A memory cell array 20 of a semiconductor device 1 is divided into four blocks consisting of a block A, block B, block C, and block D. During a period in which data read or write operations is performed for one of the blocks, refreshing is performed for the other blocks. An RF address controller 120 has a function of making logic of a signal RFA18 and a signal RFA19 among refresh address signals RFA8 to RFA19 constant so that only part of each block of the blocks A to D is refreshed in a power saving state.

Abstract: In the operation cycle, memory chip 200 initiates a refresh operation in synchronism with an external clock signal CLK after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of a clock signal CLK.

Abstract: The invention provides a semiconductor device that includes a memory cell array that is divided into four blocks. During a period in which data is read or written in one of the blocks, refreshing is conducted in all of the other remaining blocks. An ATD signal triggers a series of operations that are performed when a memory cell is read or written. Refreshing is conducted based on the ATD signal.

Abstract: In the operation cycle, memory chip 200 initiates a refresh operation in sync with an ATD signal indicating change of address after a refresh timing signal RFTM has been issued. In snooze mode (low power consumption mode), a refresh operation is initiated in response to generation of a refresh timing signal RFTM, regardless of the ATD signal.

Abstract: A semiconductor device includes a memory cell array which is divided into four blocks, specifically, a block (0), a block (1), a block (2), and a block (3). In this semiconductor device, during a period in which the data read or write is performed in one block, refreshing is executed in all of the other blocks.

Abstract: A semiconductor device includes a memory cell array which is divided into four blocks, specifically, a block (0) , a block (1), a block (2), and a block (3). In this semiconductor device, during a period in which the data read or write is performed in one block, refreshing is executed in all of the other blocks. The block (0) to block (3) are selected by an address signal A0 which is a signal of the least significant bit of the address signals and an address signal A1 which is a signal of the next least significant bit of the address signals. Since the address signal frequently changes as the bit order of the signal decreases, continuous delayed of the refreshing in one block can be prevented.