Patents by Inventor Koichi Motoyama

Koichi Motoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200118870
    Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Scott DeVries
  • Patent number: 10586767
    Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui, Ruqiang Bao, Gangadhara Raja Muthinti, Lawrence A. Clevenger
  • Patent number: 10546815
    Abstract: A method which exploits the benefits of a seed enhancement layer (in terms of void-free copper fill), while preventing copper volume loss during planarization, is provided. The method includes forming a partial seed enhancement liner in a lower portion of an opening that contains a recessed copper portion. Additional copper is formed in the upper portion of the opening providing a copper structure in which no copper volume loss at the uppermost interface of the copper structure is observed.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Oscar van der Straten, Joseph F. Maniscalco, Koichi Motoyama, Alexander Reznicek
  • Publication number: 20200027840
    Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.
    Type: Application
    Filed: July 19, 2018
    Publication date: January 23, 2020
    Applicant: International Business Machines Corporation
    Inventors: Benjamin D. BRIGGS, Cornelius Brown PEETHALA, Michael RIZZOLO, Koichi MOTOYAMA, Gen TSUTSUI, Ruqiang BAO, Gangadhara Raja MUTHINTI, Lawrence A. CLEVENGER
  • Publication number: 20200020577
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 16, 2020
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Publication number: 20200020581
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 16, 2020
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 10529622
    Abstract: Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, James J. Kelly, Hosadurga Shobha, Chih-Chao Yang
  • Publication number: 20190371735
    Abstract: A method which exploits the benefits of a seed enhancement layer (in terms of void-free copper fill), while preventing copper volume loss during planarization, is provided. The method includes forming a partial seed enhancement liner in a lower portion of an opening that contains a recessed copper portion. Additional copper is formed in the upper portion of the opening providing a copper structure in which no copper volume loss at the uppermost interface of the copper structure is observed.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Oscar van der Straten, Joseph F. Maniscalco, Koichi Motoyama, Alexander Reznicek
  • Publication number: 20190319088
    Abstract: Integrated circuits including metal-insulator-metal capacitors (MIMCAPs) generally include a diffusion barrier layer on the top and bottom surfaces of the electrode and a self-formed oxide layer on sidewalls of the electrode. The diffusion barrier layers and the self-formed oxide layers on the sidewalls of the electrode prevent diffusion of the metal defining the electrode into the interlayer dielectric. Also described are processes for fabricating the MIMCAPs.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10388600
    Abstract: A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama
  • Patent number: 10361119
    Abstract: A method is presented for forming an enlarged contact area. The method includes forming a trench for receiving a first conductive material, forming a noble metal cap over a portion of the first conductive material, forming a dielectric capping layer over the noble metal cap, etching a portion of the first conductive material to create a via anchoring structure and an undercut region exposing a bottom surface of the noble metal cap, and depositing a plurality of liners such that one liner of the plurality of liners directly contacts an entirety of the exposed bottom surface of the noble metal cap.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Chih-Chao Yang, James J. Kelly, Cornelius Brown Peethala
  • Patent number: 10340355
    Abstract: A method of forming source/drain contact structures that exhibit low contact resistance and improved electromigration properties is provided. After forming a first contact conductor portion composed of a metal having a high resistance to electromigration, such as, for example, tungsten, at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion composed of a highly conductive metal, such as, for example, copper or a copper alloy, is formed over the first contact conductor portion.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Koichi Motoyama, Oscar Van Der Straten
  • Publication number: 20190189555
    Abstract: A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: June 20, 2019
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama
  • Patent number: 10269698
    Abstract: A structure is provided that includes a lower interconnect level that includes a first interconnect dielectric material layer having an opening that contains a first bimetallization interconnect structure. An upper interconnect level is located above the lower interconnect level. The upper interconnect level includes a second interconnect dielectric material layer having a combined via/line opening, wherein the line portion of the combined via/line opening contains a second bimetallization interconnect structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama
  • Patent number: 10217664
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 10211101
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Patent number: 10204828
    Abstract: A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical dimensions. The second conductive material exhibits a lower resistivity than the first conductive material at a film thickness corresponding to the second critical dimension and the second conductive material exhibits a higher resistivity than the first conductive material at a film thickness corresponding to the first critical dimension. An initial semiconductor structure has the first trench having the first critical dimension and the second trench having the second critical dimension. The second critical dimension is larger than the first critical dimension. A first conductive structure made from one of the first and second conductive materials is formed in the first trench. A second conductive structure made from another of the first and second conductive materials is formed in the second trench.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Benjamin D. Briggs, Lawrence A. Clevenger, Koichi Motoyama, Cornelius Brown Peethala, Michael Rizzolo, Gen Tsutsui
  • Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Publication number: 20180277432
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: November 15, 2017
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Publication number: 20180277433
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang