Abstract: Methods and structures for pitch multiplication include forming a plurality of mandrel lines and non-mandrel lines on a target layer, wherein the non-mandrel lines include a protective spacer material about a top sidewall portion and a first spacer material about a lower sidewall portion, wherein the protective spacer material has a different etch selectivity than the first spacer material. The plurality of mandrel lines and non-mandrel lines are transferred into the target layer.

Abstract: Integrated circuits include back end of line metallization levels. An upper metallization level is on a lower metallization level and includes at least one top via-line interconnect structure in an interlayer dielectric. The lower metallization level includes at least one top via-line interconnect structure in an interlayer dielectric, wherein the top via is raised relative to the interlayer dielectric in the lower metallization level. The line in the upper metallization level contacts a top surface and sidewall portions of the top via raised above the interlevel dielectric. Also described are methods for fabricating the same.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.

Abstract: A dielectric spacer is formed laterally adjacent to a bottom conductive structure. The dielectric spacer is configured to limit the area in which a subsequently formed top contact structure can contact the bottom conductive structure. In some embodiments, only a topmost surface of the bottom conductive structure is contacted by the top contact structure. In other embodiments, a topmost surface and an upper sidewall surface of the bottom conductive structure is contacted by the top contact structure.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect.

Abstract: An interconnect structure, and a method for forming the same includes forming recess within a dielectric layer and conformally depositing a barrier layer within the recess. A cobalt-infused ruthenium liner is formed above the barrier layer, the cobalt containing ruthenium liner formed by stacking a second liner above a first liner, the first liner positioned above the barrier layer. The first liner includes ruthenium while the second liner includes cobalt. Cobalt atoms migrate from the second liner to the first liner forming the cobalt-infused ruthenium liner. A conductive material is deposited above the cobalt-infused ruthenium liner to fill the recess followed by a capping layer made of cobalt.

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Abstract: An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: Devices and methods that can facilitate hybrid sidewall barrier and low resistance interconnect components are provided. According to an embodiment, a device can comprise a first interconnect material layer that can have a first opening that can comprise a first discontinuous barrier liner coupled to first sidewalls of the first opening and a first continuous barrier layer coupled to the first discontinuous barrier liner and the first sidewalls. The device can further comprise a second interconnect material layer coupled to the first interconnect material layer, the second interconnect material layer can have a second opening that can comprise a second discontinuous barrier liner coupled to second sidewalls of the second opening, a second continuous barrier layer coupled to the second discontinuous barrier liner and the second sidewalls.

Abstract: A method includes forming a first metallization layer on a substrate comprising a plurality of conductive lines. The method further includes forming a first dielectric layer on the substrate and between adjacent conductive lines. The method further includes forming a first via layer comprising at least one via in the first dielectric layer and exposing a top surface of at least one of the plurality of conductive lines. The method further includes depositing a first conductive material in the first via. The method further includes forming a barrier layer on a top surface of the first dielectric layer and exposing a top surface of the plurality of conductive lines and the first conductive material.

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a fully aligned via design generally includes wide lines formed of copper and narrow lines formed of an alternative metal. The fully aligned vias are fabricated using a metal recess approach and the hybrid metal conductors can be fabricated using a selective deposition approach.

Abstract: A method includes patterning an interconnect trench in a dielectric layer. The interconnect trench has sidewalk and a bottom surface. A liner layer is deposited on the sidewalls and the bottom surface of the interconnect trench. The interconnect trench is filled with a first conductive metal material. The conducting metal material is recessed to below a top surface of the dielectric layer. A cap layer is deposited on a top surface of the first conductive metal material. The cap layer and the liner layer are of the same material. The method further includes forming a via on a portion of the interconnect trench.

Abstract: A method for manufacturing a semiconductor device includes forming first and second interconnect structures on an etch stop layer, wherein the second interconnect structure is spaced apart from the first interconnect structure. The etch stop layer extends between the first and second interconnect structures. In the method, part of the etch stop layer between the first and second interconnect structures is removed. The removing forms a first portion of the etch stop layer extending from under the first interconnect structure toward the second interconnect structure, and a second portion of the etch stop layer extending from under the second interconnect structure toward the first interconnect structure. The first and second portions are spaced apart from each other. A dielectric layer is formed which fills in the spaces between the first and second portions of the etch stop layer and between the first and second interconnect structures.

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.