Patents by Inventor Koichi Nitta

Koichi Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281526
    Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1−x−yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1−x−yN layer or a p-type InxAlyGa1−x−yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1−x−yN layer while maintaining the crystallinity of the InxAlyGa1−x−yN layer.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 28, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Haruhiko Okazaki, Tokuhiko Matsunaga
  • Patent number: 6278136
    Abstract: A light emitting element includes a multi-layered structure including an n-type nitride compound semiconductor layer and a p-type nitride compound semiconductor layer stacked on a substrate, and the multi-layered structure has formed an n-type region extending through the p-type semiconductor layer down to the n-type semiconductor layer to permit the p-side electrode and the n-side electrode to be formed on a common plane. A high-resistance region may be formed to surround the n-type region in order to more effectively block a leak current produced between the n-type region and the p-type nitride compound semiconductor. The light emitting element therefore includes no step on its surface, which simplifies the wafer process and contributes to wider applications of the semiconductor light emitting elements.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: August 21, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Nitta
  • Patent number: 6277222
    Abstract: An electronic component connecting method of connecting a first electronic component and a second electronic component via a connecting structure like a bump electrode in which a thermosetting conductive adhesive is applied on connecting electrodes on an IC chip, which serves as the first electronic component, by printing or the like, and is hardened, whereby tapered projecting electrodes as bump electrodes are formed to project in the form of, for example, a circular cone. Then, a conductive adhesive for connection is applied on the projecting electrodes. Before the conductive adhesive for connection is hardened, the IC chip is aligned with a wiring board, which serves as the second electronic component, so that the ends of the projecting electrodes and connecting electrodes on the wiring board are in contact with each other. In this aligned state, the conductive adhesive for connection is hardened.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: August 21, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Ryoichi Morimoto, Koichi Nitta
  • Patent number: 6258617
    Abstract: A gallium-nitride-based blue light emitting element that is manufacturable through a small number of processes and a method of manufacturing the same are disclosed. A first gallium-nitride-based semiconductor layer containing impurities of a first conductivity type, a gallium-nitridebased semiconductor active layer that is substantially intrinsic, and a second gallium-nitride-based semiconductor layer containing impurities of a second conductivity type that is opposite to the first conductivity type are formed according to a thermal CVD method and are left in an inert gas to cool by themselves.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Hidetoshi Fujimoto, Masayuki Ishikawa
  • Publication number: 20010003296
    Abstract: An electronic component connecting method of connecting a first electronic component and a second electronic component via a connecting structure like a bump electrode in which a thermosetting conductive adhesive is applied on connecting electrodes on an IC chip, which serves as the first electronic component, by printing or the like, and is hardened, whereby tapered projecting electrodes as bump electrodes are formed to project in the form of, for example, a circular cone. Then, a conductive adhesive for connection is applied on the projecting electrodes. Before the conductive adhesive for connection is hardened, the IC chip is aligned with a wiring board, which serves as the second electronic component, so that the ends of the projecting electrodes and connecting electrodes on the wiring board are in contact with each other. In this aligned state, the conductive adhesive for connection is hardened.
    Type: Application
    Filed: April 26, 1999
    Publication date: June 14, 2001
    Inventors: RYOICHI MORIMOTO, KOICHI NITTA
  • Patent number: 6192562
    Abstract: A piezoelectric component prevents development of a short circuit between separate electrodes of a piezoelectric element and provides a high level of connection reliability. The piezoelectric component includes a piezoelectric element utilizing a longitudinal oscillation mode and being mounted on a mounting substrate. The piezoelectric element has on one main surface thereof a first electrode and a second electrode formed by dividing electrode material via longitudinally extending linear grooves and, on the other main surface, a third electrode. Conductive support members are secured to node sections of the first and second electrodes so as to be spaced apart from each other with respect to the longitudinal dimension of the piezoelectric substrate. The support members are adhered to and secured to pattern electrodes of the mounting substrate by conductive adhesive.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: February 27, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Motoyuki Okeshi, Yasuo Otowaki, Koichi Nitta, Satoru Hachinohe, Takashi Hashimoto, Makoto Irie
  • Patent number: 6158098
    Abstract: A piezoelectric element prevents the development of a short circuit between separate electrodes and provides a high level of connection reliability. The piezoelectric element utilizing a longitudinal oscillation mode includes a piezoelectric substrate which has on one main surface thereof a first electrode and a second electrode separated by longitudinally extending linear grooves and, on the other main surface, a third electrode. Conductive support members are secured to node sections of the first and second electrodes so as to be spaced apart from each other with respect to the longitudinal dimension of the piezoelectric substrate.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: December 12, 2000
    Assignee: Murata Manufacturing Co. LTD
    Inventors: Motoyuki Okeshi, Yasuo Otowaki, Koichi Nitta, Satoru Hachinohe, Takashi Hashimoto, Makoto Irie
  • Patent number: 6047603
    Abstract: An ultrasonic sensor includes: a floored cylindrical case, a piezoelectric vibration element and input-output terminals. The floored cylindrical case has a separately prepared cylinder part and a separately prepared vibration part, and the cylinder part and the vibration part are adhered together with an adhesive material having an elastic modulus in the range from 100 through 20,000 kgf/mm.sup.2 at a temperature range from 25 through 125.degree. C. The piezoelectric vibration element is disposed on the inner bottom floor of the floored cylindrical case. The input-output terminals are electrically connected to the piezoelectric vibration element and are adapted for electrical connection to outside of the floored cylindrical case.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: April 11, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shozo Ohtera, Hidetoshi Iwatani, Satoru Hachinohe, Koichi Nitta
  • Patent number: 6005330
    Abstract: A piezoelectric component prevents development of a short circuit between separate electrodes of a piezoelectric element and provides a high level of connection reliability. The piezoelectric component includes a piezoelectric element utilizing a longitudinal oscillation mode and being mounted on a mounting substrate. The piezoelectric element has on one main surface thereof a first electrode and a second electrode formed by dividing electrode material via longitudinally extending linear grooves and, on the other main surface, a third electrode. Conductive support members are secured to node sections of the first and second electrodes so as to be spaced apart from each other with respect to the longitudinal dimension of the piezoelectric substrate. The support members are adhered to and secured to pattern electrodes of the mounting substrate by conductive adhesive.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: December 21, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Motoyuki Okeshi, Yasuo Otowaki, Koichi Nitta, Satoru Hachinohe, Takashi Hashimoto, Makoto Irie
  • Patent number: 5977565
    Abstract: A semiconductor light emitting diode having a high surge resistance and high reliability has a structure which includes an additional capacitor formed between an anode and a cathode of the light emitting element. Specifically, in an LED having an n-type GaN semiconductor layer, a GaN-based active layer and a p-type GaN-based semiconductor layer on a sapphire substrate, the cathode is formed on the n-type GaN semiconductor layer and an electrode wiring extends from the top of the p-type GaN-based semiconductor layer to form a capacitor.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: November 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Koichi Nitta
  • Patent number: 5900650
    Abstract: There is disclosed a semiconductor device formed on a sapphire substrate, for example, a blue LED of a double-hetero structure having a laminated structure which comprises a first cladding layer made of a first conductivity type gallium nitride based semiconductor, an active layer made of a gallium nitride based semiconductor into which impurity is not doped intentionally, and a second cladding layer made of a second conductivity type gallium nitride based semiconductor which being opposite to the first conductivity type on a sapphire substrate. A surface of the sapphire substrate is polished to have optical transmissivity of more than 60%.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: May 4, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Nitta
  • Patent number: 5859488
    Abstract: A piezoelectric element prevents the development of a short circuit between separate electrodes and provides a high level of connection reliability. The piezoelectric element utilizing a longitudinal oscillation mode includes a piezoelectric substrate which has on one main surface thereof a first electrode and a second electrode separated by longitudinally extending linear grooves and, on the other main surface, a third electrode. Conductive support members are secured to node sections of the first and second electrodes so as to be spaced apart from each other with respect to the longitudinal dimension of the piezoelectric substrate.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: January 12, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Motoyuki Okeshi, Yasuo Otowaki, Koichi Nitta, Satoru Hachinohe, Takashi Hashimoto, Makoto Irie
  • Patent number: 5798537
    Abstract: There is disclosed a blue light emitting device having a laminated structure, which comprises a buffer layer made of a first conductivity type GaN-based semiconductor, a first cladding layer made of the first conductivity type GaN-based semiconductor, an active layer made of a substantially intrinsic GaN-based semiconductor, and a second cladding layer made of a second conductivity type GaN-based semiconductor, on a conductive substrate such as a conductive sapphire substrate. The GaN-based semiconductors of the present invention are made of quaternary compound semiconductor layers, and preferably made of In.sub.x A.sub.y Ga.sub.1-x-y N whose mole fraction values x, y satisfy 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1 and x+y.ltoreq.1. The mole fraction values x, y are selected to obtain desired luminous wavelength and intensity.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: August 25, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Nitta
  • Patent number: 5789265
    Abstract: A method of manufacturing blue light-emitting device is disclosed wherein a laminated structure comprising a p-type In.sub.x Al.sub.y Ga.sub.1-x-y N layer and an n-type In.sub.x Al.sub.y Ga.sub.1-x-y N layer are etched selectively by virtue of a parallel plate type plasma etching (RIE) using etching gas including boron trichloride (BCl.sub.3) and chlorine (Cl.sub.2).
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: August 4, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Sumio Ishimatsu
  • Patent number: 5696389
    Abstract: A light-emitting semiconductor device comprising an n-type cladding layer provided on a surface of a substrate and having concentric first and second parts, a first electrode mounted on the first part of the n-type cladding layer, a p-type cladding layer provided above the surface of the substrate and surrounding the first electrode and the second part of the n-type cladding layer, and a second electrode provided on the p-type cladding layer.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: December 9, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Hideto Sugawara, Yukie Nishikawa, Masaaki Onomura, Shinji Saito, Peter James Parbrook, Genichi Hatakoshi, Koichi Nitta, John Rennie, Hiroaki Yoshida, Atsushi Kamata
  • Patent number: 5693963
    Abstract: A light emitting diode is arranged on a sapphire substrate. The light emitting diode includes an n-GaN layer, an n-InGaN light-emitting layer, a p-AlGaN layer and a P-GaN layer, which are grown through vapor phase growth in this sequence. Within the p-GaN layer and p-AlGaN layer, 1.times.10.sup.20 cm.sup.-3 of Mg and 2.times.10.sup.19 cm.sup.-3 of Mg are contained, respectively. Within each of the n-GaN layer and n-InGaN light-emitting layer, 5.times.10.sup.18 cm.sup.-3 of hydrogen is contained, thereby preventing Mg from diffusing therein from the p-GaN layer and p-AlGaN layer.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: December 2, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Fujimoto, Koichi Nitta, Masayuki Ishikawa, Hideto Sugawara, Yoshihiro Kokubun, Masahiro Yamamoto
  • Patent number: 5488233
    Abstract: This invention provides a semiconductor light-emitting device including a semiconductor substrate consisting of a compound semiconductor of elements in the third and fifth groups of the period table, a first compound semiconductor layer formed directly on at least a portion of the semiconductor substrate and consisting of a compound semiconductor containing at least In and P, and a second compound semiconductor formed directly on the first compound semiconductor layer and consisting of a compound semiconductor of elements in the second and sixth groups of the periodic table. With this arrangement, it is possible to sufficiently prevent the occurrence of defects in the interface between the semiconductor substrate and the second compound semiconductor layer consisting of the compound semiconductor of the elements in the second and sixth groups of the periodic table.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Yukie Nishikawa, Shinji Saito, Peter J. Parbrook, Masaaki Onomura, Koichi Nitta, Genichi Hatakoshi
  • Patent number: 5424093
    Abstract: A thick layer of electrode material paint is formed on a flat surface. A film of the electrode material paint is formed on an element by dipping the element into the layer. In the next step, a thinner layer of the electrode material paint than the aforementioned layer is formed on a flat surface. Into the thinner layer of the electrode material paint, the film of the electrode material paint formed on the element is dipped. Alternatively, the element may first be dipped into a thinner layer of the electrode material paint so that a thin film of the electrode material paint is formed on the element. The film formed on the element is then dipped into a thick layer of the electrode material paint and then again into a thin layer of the electrode material paint in such order. By firing the film of the electrode material paint obtained in this manner, an electronic element having external electrodes of a uniform thickness can be obtained.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: June 13, 1995
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Koichi Nitta, Michio Kaeriyama, Kazuma Kabuta, Haruo Hori, Masami Yamaguchi, Tadahiro Nakagawa
  • Patent number: 5343486
    Abstract: According to this invention, a semiconductor laser device includes a compound semiconductor substrate, a double hetero structure formed on the compound semiconductor substrate and having an active layer and first and second cladding layers which interpose the active layer, a current blocking region formed in one facet portion of the double hetero structure in a resonator direction. A reflecting layer is arranged on the other facet of the double hetero structure in the resonator direction and has a reflectance higher than that of a natural cleavage surface, thereby shifting the oscillation wavelength of the laser device to a long wavelength side with respect to the wavelength of spontaneous radiation emitted from one facet of the double hetero structure.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: August 30, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Genichi Hatakoshi, Koichi Nitta
  • Patent number: 5321712
    Abstract: A semiconductor light-emitting element includes a semiconductor substrate of a first conductivity type, a lower cladding layer formed on the semiconductor substrate and constituted by an InGaAlP-based compound of the first conductivity type, an active layer formed on the lower cladding layer, and constituted by a material selected from the group consisting of GaAs, GaAlAs, and InGaAs, and an upper cladding layer formed on the active layer, and constituted by the InGaAlP-based compound of a second conductivity type, wherein the InGaAlP-based compound is represented by a formula In.sub.y (Ga.sub.1-x Al.sub.x).sub.y P, where x is in the range of 0.3 to 0.7 and y is in the range of 0.45 to 0.55.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: June 14, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Koichi Nitta, Genichi Hatakoshi, Yukie Nishikawa, Hideto Sugawara, Mariko Suzuki